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參數(shù)資料
| 型號(hào)： | 82439TX |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲(chǔ)控制器/管理單元 |
| 英文描述： | System Controller(系統(tǒng)控制器) |
| 中文描述： | 256M X 8, DRAM CONTROLLER, PBGA324 |
| 封裝： | BGA-324 |
| 文件頁數(shù)： | 59/83頁 |
| 文件大?。?/td> | 461K |
| 代理商： | 82439TX |
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E
4.3.6.
82439TX (MTXC)
59
PRELIMINARY
AUTO DETECTION
The SDRAM, FPM, and EDO detection is performed by BIOS. Note that when accessing any of the DRAM
related registers (i.e., 54h–68h), refresh should be turned off via the DRAM Control register (DRAMC).
4.3.7.
DRAM PERFORMANCE
The DRAM performance is controlled by the DRAM timing register, processor pipelining, and by the type of
DRAM used (EDO or FPM or SDRAM). Table 17 depicts both EDO and standard page mode optimum timings.
For read cycles, clocks counts are measured from ADS# to BRDY#.
For write cycles, the measurement is broken up into two parts. The first part consists of the rate of posting data
in to the CPU to DRAM posted write buffers. This is measured from ADS# to BRDY#. The second part consists
of the retire rate from posted write buffers to the DRAM. The leadoff for retiring is measured from the clock after
BRDY# assertion to the CAS# assertion.
Table 17 lists the performance summary for 60 ns EDO/FPM DRAMs. The four row column is assuming each
row is populated with a maximum of 16, x4 devices=64 DRAM devices. The five row column is assuming each of
the first four rows is populated with a maximum of 16, x4 devices and the fifth row is populated with a maximum
of eight, x8 devices=72 DRAM devices. The six row column assumes that each of the six rows can be populated
with a maximum of 16, x4 devices.
The FELO and SLD bits are used to control the leadoff for read cycles (page hit, row miss, and page miss). Each
bit removes one clock from the leadoff, when enabled. Note that FELO impacts EDO only and must be disabled
for FPM. The DLT bits are used to control the base starting point for the leadoff for read/write cycles (page miss
and row miss, only).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 82443MX | PCIset |
| 82443ZX | Intel㈢ 440ZX AGPset: Host Bridge/Controller |
| 82451NX | Intel 450NX PCIset |
| 82452NX | Intel 450NX PCIset |
| 82453NX | Intel 450NX PCIset |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82439TXC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:INTEL 430HX PCISET 82439HX SYSTEM CONTROLLER (TXC) |
| 8243-A-0632-0 | 制造商:AMATOM ELECTRONIC HARDWARE 功能描述: |
| 8243-W | 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類別:靜電控制，ESD，無塵室產(chǎn)品 >> 處理劑，清潔劑，擦拭布 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 處理劑/清潔劑類型:清潔布 使用:電子設(shè)備 技術(shù)規(guī)格:無絨毛，微纖維 數(shù)量:100（12" L x 12" W） 包裝:袋 |
| 8243-W X(25) | 功能描述:化學(xué)物質(zhì) OPTICAL WIPE 25 PER BOX RoHS:否 制造商:3M Electronic Specialty 產(chǎn)品:Adhesives 類型:Epoxy Compound 大小:1.7 oz 外殼:Plastic Tube |
| 8243-WX25 | 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類別:靜電控制，ESD，無塵室產(chǎn)品 >> 處理劑，清潔劑，擦拭布 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 處理劑/清潔劑類型:清潔布 使用:電子設(shè)備 技術(shù)規(guī)格:無絨毛，微纖維 數(shù)量:100（12" L x 12" W） 包裝:袋 |
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