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參數(shù)資料
| 型號： | 82439TX |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | System Controller(系統(tǒng)控制器) |
| 中文描述： | 256M X 8, DRAM CONTROLLER, PBGA324 |
| 封裝： | BGA-324 |
| 文件頁數(shù)： | 24/83頁 |
| 文件大?。?/td> | 461K |
| 代理商： | 82439TX |
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82439TX (MTXC)
E
24
PRELIMINARY
Bit
Description
2
Bus Master Enable (BME)
.
(Not implemented)
This bit is hardwired to 1. The MTXC does not
support disabling of its bus master capability on the PCI Bus.
1
Memory Access Enable (MAE)
.
When MAE=1, the MTXC permits PCI masters to access main
memory if the PCI address selects enabled DRAM space. When MAE=0, the MTXC does not
respond to main memory accesses.
0
I/O Access Enable (IOAE)
.
(Not implemented)
The MTXC does not respond to PCI I/O cycles.
This bit is hardwired to 0.
3.1.7.
PCISTS
PCI STATUS REGISTER
Address Offset:
Default Value:
Access:
06–07h
0200h
Read Only, Read/Write Clear
PCISTS is a 16-bit status register that reports the occurrence of a PCI master abort and PCI target abort.
PCISTS also indicates the DEVSEL# timing that has been set by the MTXC hardware.
Bit
Description
15
Detected Parity Error (DPE).
This bit is hardwired to 0, as PCI received parity checking is not
implemented by the MTXC.
14
Signaled System Error (SSE).
This bit is hardwired to 0 as MTXC does not support SERR#.
13
Received Master Abort Status (RMAS).
When the MTXC terminates a Host-to-PCI transaction
(MTXC is a PCI master) with an unexpected master abort, this bit is set to 1. Note that master abort
is the normal and expected termination of PCI special cycles. Software resets this bit to 0 by writing
a 1 to it.
12
Received Target Abort Status (RTAS).
When a MTXC-initiated PCI transaction is terminated with
a target abort, RTAS is set to 1. Software resets RTAS to 0 by writing a 1 to it.
11
Signaled Target Abort Status (STAS).
This bit is hardwired to 0, as the MTXC never terminates a
PCI cycle with a target abort.
10:9
DEVSEL# Timing (DEVT)
.
This 2-bit field indicates the timing of the DEVSEL# signal when the
MTXC responds as a target, and is hardwired to the value 01b (medium) to indicate the slowest time
that DEVSEL# is generated.
8
Data Parity Detected (DPD)
.
This bit is hardwired to 0, as PERR# is not implemented.
7
Fast Back-to-Back (FB2B).
This bit is hardwired to 0, as fast back to back cycle generation is not
implemented.
6
User Defined Format (UDF).
This bit is hardwired to 0. This is because the MTXC does not contain
any configurations that depend on the environment, such as network frequencies.
5
66-MHz PCI Capable (66C).
This bit is hardwired to 0. The MTXC does not interface to 66-MHz PCI.
4:0
Reserved
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 82443MX | PCIset |
| 82443ZX | Intel㈢ 440ZX AGPset: Host Bridge/Controller |
| 82451NX | Intel 450NX PCIset |
| 82452NX | Intel 450NX PCIset |
| 82453NX | Intel 450NX PCIset |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82439TXC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:INTEL 430HX PCISET 82439HX SYSTEM CONTROLLER (TXC) |
| 8243-A-0632-0 | 制造商:AMATOM ELECTRONIC HARDWARE 功能描述: |
| 8243-W | 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類別:靜電控制，ESD，無塵室產(chǎn)品 >> 處理劑，清潔劑，擦拭布 系列:- 標準包裝:100 系列:- 處理劑/清潔劑類型:清潔布 使用:電子設備 技術(shù)規(guī)格:無絨毛，微纖維 數(shù)量:100（12" L x 12" W） 包裝:袋 |
| 8243-W X(25) | 功能描述:化學物質(zhì) OPTICAL WIPE 25 PER BOX RoHS:否 制造商:3M Electronic Specialty 產(chǎn)品:Adhesives 類型:Epoxy Compound 大小:1.7 oz 外殼:Plastic Tube |
| 8243-WX25 | 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類別:靜電控制，ESD，無塵室產(chǎn)品 >> 處理劑，清潔劑，擦拭布 系列:- 標準包裝:100 系列:- 處理劑/清潔劑類型:清潔布 使用:電子設備 技術(shù)規(guī)格:無絨毛，微纖維 數(shù)量:100（12" L x 12" W） 包裝:袋 |
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