參數(shù)資料
型號: 82439TX
廠商: INTEL CORP
元件分類: 存儲控制器/管理單元
英文描述: System Controller(系統(tǒng)控制器)
中文描述: 256M X 8, DRAM CONTROLLER, PBGA324
封裝: BGA-324
文件頁數(shù): 25/83頁
文件大?。?/td> 461K
代理商: 82439TX
E
3.1.8.
82439TX (MTXC)
25
PRELIMINARY
RID
REVISION IDENTIFICATION REGISTER
Address Offset:
Default Value:
Access:
08h
01h
Read Only
This register contains the revision number of the MTXC. These bits are read only and writes to this register have
no effect.
Bit
Description
7:0
Revision Identification Number.
This is an 8-bit value that indicates the revision identification
number for the MTXC.
3.1.9.
CLASSC
CLASS CODE REGISTER
Address Offset:
Default Value:
Access:
09
0Bh
00h
Read Only
This register contains the device programming interface information related to the Sub-Class Code and Base
Class Code definition for the MTXC. This register also contains the Base Class Code and the function
sub-class in relation to the Base Class Code.
Bit
Description
23:16
Base Class Code (BASEC).
06=Bridge device.
15:8
Sub-Class Code (SCC).
00h=Host Bridge.
7:0
Programming Interface (PI).
00h=Hardwired as a Host-to-PCI Bridge.
3.1.10.
MLT
MASTER LATENCY TIMER REGISTER
Address Offset:
Default Value:
Access:
0Dh
00h
Read/Write
MLT is an 8-bit register that controls the amount of time the MTXC, as a bus master, can burst data on the PCI
Bus. The Count Value is an 8-bit quantity. However MLT[2:0] are reserved and assumed to 0 when determining
the Count Value. MLT is used to guarantee the host CPU a minimum amount of the system resources.
The number of clocks programmed in the MLT represents the guaranteed time slice (measured in PCI clocks)
allotted to the MTXC, after which it must surrender the bus as soon as other PCI masters request the bus. The
default value of MLT is 00h or 0 PCI clocks.
Bit
Description
7:3
Master Latency Timer Count Value
2:0
Reserved.
Read as 0s
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參數(shù)描述
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