參數(shù)資料
型號： 82439TX
廠商： INTEL CORP
元件分類： 存儲控制器/管理單元
英文描述： System Controller(系統(tǒng)控制器)
中文描述： 256M X 8, DRAM CONTROLLER, PBGA324
封裝： BGA-324
文件頁數(shù)： 10/83頁
文件大?。?/td> 461K
代理商： 82439TX
82439TX (MTXC)
E
10
PRELIMINARY
2.1.2.
DRAM INTERFACE
Name
Type
Description
RAS[3:0]#
or
CS[3:0]#,
RAS4#/CS4#/
BA1,
RAS5#/CS5#/
MA13
O
3.3 V
Row Address Strobe—RASx# (EDO/FPM).
These pins select the DRAM row.
Chip Select—CSx# (SDRAM).
These pins activate the SDRAMs. SDRAM accepts
any command when its CS# pin is active low.
Note: For 64Mbit SDRAM support, BA1/MA12 and MA13 are muxed with the
RAS4# and RAS5# signals, respectively. When SDRAMC[bit 1]=1, BA1 and MA13
are driven out on these lines.
CAS[7:0]# or
DQM[7:0]
O
3.3 V
Column Address Strobe (EDO/FPM).
These pins select the DRAM column.
Input/Output Data Mask SDRAM).
These pins act as synchronized output enables
during a read cycle and a byte mask during a write cycle. The read cycles require
Tdqz clock latency before the functions are actually performed. In case of a write
cycle, word mask functions are performed in the same cycle (0 cycle latency).
MA[11:0]
O
3.3 V
Memory Address (EDO/FPM/SDRAM).
This is the row and column address for
DRAM. These buffers now include programmable size selection, as controlled by
the DRAMEC[MAD] bit. For 64-Mbit SDRAM support BA1/MA12 and MA13 are
muxed with the RAS4# and RAS5# signals, respectively.
MWEB#
O
3.3 V
Memory Write Enable (second copy) (EDO/FPM/SDRAM).
MWE# should be
used as the write enable for the memory data bus. This signal has programmable
buffer size selection.
MWE#
O
3.3 V
Memory Write Enable (EDO/FPM/SDRAM).
MWE# should be used as the write
enable for the memory data bus. This signal has programmable buffer size
selection.
SRAS[A,B]#
O
3.3 V
SDRAM Row Address Strobe (SDRAM).
When asserted, this signal latches Row
Address on the positive edge of the clock. This signal also allows Row access and
precharge. Two copies are provided for loading purpose. These signals have
programmable buffer size selection.
SCAS[A,B]#
O
3.3 V
SDRAM Column Address Strobe (SDRAM).
When asserted, this signal latches
Column Address on the positive edge of the clock. This signal also allows Column
access. Two copies provided for loading purpose. These signals have
programmable buffer size selection.
CKE/MAA0
O
3.3 V
SDRAM Clock Enable (SDRAM).
SDRAM
clock enable pin. When this signal is
negated, SDRAM enters power down mode. This signal is also muxed to provide a
second copy of memory address MA0 (MAA0). The MA function is selected via
DRT[bit2] (offset 67h).
MTXC negates CKE (and CKEB) when SUSSTAT1# is asserted. Note that MTXC
asserts CKE (and CKEB) for all rows (i.e., CKE and CKEB cannot be selectively
asserted for certain rows and negated for other rows).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
82439TXC 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:INTEL 430HX PCISET 82439HX SYSTEM CONTROLLER (TXC)
8243-A-0632-0 制造商:AMATOM ELECTRONIC HARDWARE 功能描述:
8243-W 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類別:靜電控制，ESD，無塵室產(chǎn)品 >> 處理劑，清潔劑，擦拭布 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 處理劑/清潔劑類型:清潔布 使用:電子設(shè)備 技術(shù)規(guī)格:無絨毛，微纖維 數(shù)量:100（12" L x 12" W） 包裝:袋
8243-W X(25) 功能描述:化學(xué)物質(zhì) OPTICAL WIPE 25 PER BOX RoHS:否 制造商:3M Electronic Specialty 產(chǎn)品:Adhesives 類型:Epoxy Compound 大小:1.7 oz 外殼:Plastic Tube
8243-WX25 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類別:靜電控制，ESD，無塵室產(chǎn)品 >> 處理劑，清潔劑，擦拭布 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 處理劑/清潔劑類型:清潔布 使用:電子設(shè)備 技術(shù)規(guī)格:無絨毛，微纖維 數(shù)量:100（12" L x 12" W） 包裝:袋
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