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參數(shù)資料
| 型號(hào)： | 82439TX |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲(chǔ)控制器/管理單元 |
| 英文描述： | System Controller(系統(tǒng)控制器) |
| 中文描述： | 256M X 8, DRAM CONTROLLER, PBGA324 |
| 封裝： | BGA-324 |
| 文件頁數(shù)： | 79/83頁 |
| 文件大?。?/td> | 461K |
| 代理商： | 82439TX |
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E
8.0.
82439TX (MTXC)
79
PRELIMINARY
TESTABILITY
8.1.
NAND Tree Mode
A NAND tree mode is provided for Automated Test Equipment (ATE) board level testing. The NAND tree allows
the tester to set the connectivity of each of the MTXC’s signal pins. In Mobile/desktop mode, the NAND tree
mode is activated by driving the test pin TEST# low when REQx# pins are at 0010. If TEST# is negated at any
time, the test mode is deactivated and the MTXC goes back to normal operation. There is no guarantee that
upon re-entering normal operation the chip will function properly, if the test mode was entered while the MTXC
was not in a completely idle state.
The MTXC has several test modes to improve board manufacturing. If the TEST# signal is asserted (driven low),
the value on the REQ[3:0]# indicates the test mode to enable. The test mode enabled at the falling edge of
TEST# will remain enabled until TEST# is negated.
Table 25 shows each test mode and the value of REQ#[3:0] required to enable it. All other values of REQ[3:0]#
while TEST# is active, are reserved and should not be asserted by the customer.
Table 25. Test Modes
REQ[3:0]#
TEST#
PHLD#
TEST Mode
Description
0010
0
x
NAND Chain
Float outputs, enable NAND chains on GNT[3:0]#
1110
0
1
ID/REV code
Drives Device ID on AD[31:16] and revision ID on
AD[7:0]
1110
0
0
MID Code
Drives Manufacture ID on AD[31:0]
1111
0
x
Disable test
mode
1
Disables any active test mode, puts MTXC back into
normal mode
NOTES:
1.
It is recommended to assert RST# if this mode is used, to guarantee pins and PCIset will function normally.
8.2.
NAND Chain Mode
In NAND Tree mode, all outputs are tri-stated, except for GNT#[3:0]. These pins contain the NAND Chain. Note,
also, that the internal pull-ups and pull-downs are still active. Because of the 282 pins in the NAND Chain, it must
be separated into 4 chains. Two chains contain 72 pins each, 1 chain contains 70 pins, and 1 chain contains 68
pins. The MTXC remains in this mode until a new test mode is selected or RST# is asserted. The HCLK and
PCLK are part of the NAND Chain and
must
be deactivated during this test.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 82443MX | PCIset |
| 82443ZX | Intel㈢ 440ZX AGPset: Host Bridge/Controller |
| 82451NX | Intel 450NX PCIset |
| 82452NX | Intel 450NX PCIset |
| 82453NX | Intel 450NX PCIset |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82439TXC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:INTEL 430HX PCISET 82439HX SYSTEM CONTROLLER (TXC) |
| 8243-A-0632-0 | 制造商:AMATOM ELECTRONIC HARDWARE 功能描述: |
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