參數(shù)資料
型號(hào)： 82439TX
廠商： INTEL CORP
元件分類： 存儲(chǔ)控制器/管理單元
英文描述： System Controller(系統(tǒng)控制器)
中文描述： 256M X 8, DRAM CONTROLLER, PBGA324
封裝： BGA-324
文件頁(yè)數(shù)： 34/83頁(yè)
文件大?。?/td> 461K
代理商： 82439TX
82439TX (MTXC)
E
34
PRELIMINARY
Bit
Description
1:0
DRAM Leadoff Timing (DLT)
.
The DRAM leadoff timings are controlled by the DLT bits. Slower
leadoffs may be required in certain system designs to support loose layouts or slower memories.
The Row Miss leadoff timings are summarized below for EDO/FPM reads and writes.
Changing DLT affects the Row Miss and Page Miss timings only (e.g., DLT=01 is one clock faster
than DLT=00 on Row Miss and Page Miss timings). These bit control MA setup to CAS# assertion.
DLT does not affect page hit timings. Thus, DLT=00 or DLT=01 has same page hit timings for reads
and writes (e.g., for reads, it would be 10-3=7 clocks for DLT=00 or DLT=01)
DLT
Read Leadoff
Write Leadoff
RAS# Precharge
00
11
7
01
10
6
10
11
7
11
10
6
SLD and FELO bits have cumulative effect on the leadoff timings. The above leadoff represent
timings with SLD=1 and FELO=0.
RAS-to-CAS Delay
4
3
4
3
3
3
4
4
3.1.21.
PAM
PROGRAMMABLE ATTRIBUTE MAP REGISTERS (PAM[6:0])
Address Offset:
Default Value:
Attribute:
Size:
59h (PAM0) (5Fh (PAM6)
00h
Read/Write
8 bits (each register)
The MTXC allows programmable memory and cacheability attributes on 14 memory segments of various sizes
in the 640-Kbytes to 1-Mbyte address range. Seven Programmable Attribute Map (PAM) Registers are used to
support these features. Three bits are used to specify L1 cacheability and memory attributes for each memory
segment. These attributes are:
RE
Read Enable
. When RE=1, the CPU read accesses to the corresponding memory segment are
directed to main memory. Conversely, when RE=0, the CPU read accesses are directed to PCI.
WE
Write Enable
. When WE=1, the CPU write accesses to the corresponding memory segment are
directed to main memory. Conversely, when WE=0, the CPU write accesses are directed to PCI.
CE
Cache Enable
. When CE=1, the corresponding memory segment is L1 cacheable. CE must not be set
to 1 when RE is reset to 0 for any particular memory segment. When CE=1 and WE=0, the
corresponding memory segment is cached in the first level cache only on CPU code read cycles.
The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write, or disabled. For
example, if a memory segment has RE=1 and WE=0, the segment is Read Only. The characteristics for memory
segments with these read/write attributes are described in Table 5.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
82439TXC 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:INTEL 430HX PCISET 82439HX SYSTEM CONTROLLER (TXC)
8243-A-0632-0 制造商:AMATOM ELECTRONIC HARDWARE 功能描述:
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