參數(shù)資料
型號： 82439TX
廠商： INTEL CORP
元件分類： 存儲控制器/管理單元
英文描述： System Controller(系統(tǒng)控制器)
中文描述： 256M X 8, DRAM CONTROLLER, PBGA324
封裝： BGA-324
文件頁數(shù)： 13/83頁
文件大小： 461K
代理商： 82439TX
E
2.1.4.
82439TX (MTXC)
13
PRELIMINARY
PCI INTERFACE
Name
Type
Description
AD[31:0]
I/O
3.3/5V
Address/Data.
The standard PCI address and data lines. Address is driven with
FRAME# assertion, data is driven or received in following clocks.
C/BE[3:0]#
I/O
3.3/5V
Command/Byte Enable.
The command is driven with FRAME# assertion, byte
enables corresponding to supplied or requested data is driven on following clocks.
FRAME#
I/O
3.3/5V
Frame.
Assertion indicates the address phase of a PCI transfer. Negation indicates
that one more data transfer is desired by the cycle initiator.
DEVSEL#
I/O
3.3/5V
Device Select.
This signal is driven by the MTXC when a PCI initiator is attempting
to access DRAM. DEVSEL# is asserted at medium decode time.
IRDY#
I/O
3.3/5V
Initiator Ready.
Asserted when the initiator is ready for a data transfer.
TRDY#
I/O
3.3/5V
Target Ready.
Asserted when the target is ready for a data transfer.
STOP#
I/O
3.3/5V
Stop.
Asserted by the target to request the master to stop the current transaction.
LOCK#
I/O
3.3/5V
Lock.
Used to establish, maintain, and release resource locks on PCI.
REQ[3:0]#
I
3.3/5V
PCI Request.
PCI master requests for PCI bus.
GNT[3:0]#
O
3.3V
PCI Grant.
Permission is given to the master to use PCI.
PHLD#
I
3.3/5V
PCI Hold.
This signal comes from the expansion bridge. It is the bridge request for
PCI. The MTXC will drain the DRAM write buffers, drain the CPU-to-PCI posting
buffers, and acquire the host bus before granting via PHLDA#.
PHLDA#
O
3.3V
PCI Hold Acknowledge.
This signal is driven by the MTXC to grant PCI to the
expansion bridge. PHLDA# protocol has been modified to include support for
passive release.
PAR
I/O
3.3/5V
Parity.
A single parity bit is provided over AD[31:0] and C/BE[3:0]. This signal
should be pulled high through a weak external pull-up resistor.
CLKRUN#
I/O
3.3/5V
CLOCK RUN.
An open drain output and also an input. MTXC requests the central
resource (PIIX4) to start, or maintain the PCI clock by the assertion of CLKRUN#.
MTXC will tri-state CLKRUN# upon negation of reset (since CLK is running upon
negation of reset). External pull-up is required. Note: This signal should be
connected to the PIIX4 CLKRUN# pin. However, if it is left as a no connect on the
MTXC, it must be pulled low through a 100
(pull-down resistor.
RST#
I
3.3/5V
Reset.
When asserted this signal asynchronously resets the MTXC. The PCI
signals also tri-state compliant to PCI Rev 2.0 and 2.1 specifications.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
82439TXC 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:INTEL 430HX PCISET 82439HX SYSTEM CONTROLLER (TXC)
8243-A-0632-0 制造商:AMATOM ELECTRONIC HARDWARE 功能描述:
8243-W 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類別:靜電控制，ESD，無塵室產(chǎn)品 >> 處理劑，清潔劑，擦拭布 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 處理劑/清潔劑類型:清潔布 使用:電子設(shè)備 技術(shù)規(guī)格:無絨毛，微纖維 數(shù)量:100（12" L x 12" W） 包裝:袋
8243-W X(25) 功能描述:化學(xué)物質(zhì) OPTICAL WIPE 25 PER BOX RoHS:否 制造商:3M Electronic Specialty 產(chǎn)品:Adhesives 類型:Epoxy Compound 大小:1.7 oz 外殼:Plastic Tube
8243-WX25 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類別:靜電控制，ESD，無塵室產(chǎn)品 >> 處理劑，清潔劑，擦拭布 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 處理劑/清潔劑類型:清潔布 使用:電子設(shè)備 技術(shù)規(guī)格:無絨毛，微纖維 數(shù)量:100（12" L x 12" W） 包裝:袋
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