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參數(shù)資料
| 型號： | 82439TX |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | System Controller(系統(tǒng)控制器) |
| 中文描述： | 256M X 8, DRAM CONTROLLER, PBGA324 |
| 封裝： | BGA-324 |
| 文件頁數(shù)： | 12/83頁 |
| 文件大?。?/td> | 461K |
| 代理商： | 82439TX |
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82439TX (MTXC)
E
12
PRELIMINARY
2.1.3.
SECONDARY CACHE INTERFACE
Name
Type
Description
CADV#
O
3.3V
Cache Advance.
Assertion causes the PBSRAM in the secondary cache to
advance to the next QWord in the cache line.
CADS#
O
3.3V
Cache Address Strobe.
Assertion causes the PBSRAM in the secondary
cache to load the PBSRAM address register from the PBSRAM address pins.
CCS#
O
3.3V
Cache Chip Select (CCS#).
The second level cache will power up, if
necessary, and perform an access if this signal is asserted when CADS# is
asserted. The second level cache will power down if this signal is negated when
CADS# is asserted. When CCS# is negated the second level cache will ignore
ADS#. If CCS# is asserted when ADS# is asserted, the second level cache will
power up, if necessary, and perform an access.
COE#
O
3.3V
Cache Output Enable.
The secondary cache data RAMs drive the CPUs data
bus when COE# is asserted.
GWE#
O
3.3V
Global Write Enable.
GWE# assertion causes all the byte lanes to be written
into the secondary cache data RAMs, if they are powered up.
BWE#
O
3.3V
Byte Write Enable.
Asserted low with GWE#=HIGH to enable using host’s
BE[7:0]# to be used to control byte lanes to pipeline burst SRAM cache.
TIO[7:0]
I/O
3.3V/5V
Tag Address.
These are inputs during CPU accesses and outputs during
second level cache line fills and second level cache line invalidates due to
inquire cycles. These signals have internal pull-down resistors.
TWE#
O
3.3V
Tag Write Enable.
When asserted, new state and tag addresses are written
into the external tag.
KRQAK/
CS4_64#
I/O
3.3V
KRQAK/Chip Select 4 (for 64-Mb Technology).
This pin is a dual-function
signal. KRQAK is used in a DRAM Cache L2 implementation and is a
bi-directional refresh request/acknowledge. The CS4_64# function is used
to generate the fifth chip select line in a SDRAM L2 Cache implementation
that supports five rows of 64-Mbit SDRAM.
During a hard reset, this signal is sampled to determine if DRAM cache is in
the system (see MTXC Strapping options). This signal has a weak internal
pull-down.
If SDRAMC[bit 1]=1 and DRAM cache is not present in the system (indicated by
CEC[bit 5]=0, offset 53h), the CS4_64# function is selected. If DRAM cache is in
the system or SDRAMC[bit 1] (offset 54h)=0, then KRQAK is used to drive the
KRQAK function.
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| 82453NX | Intel 450NX PCIset |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82439TXC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:INTEL 430HX PCISET 82439HX SYSTEM CONTROLLER (TXC) |
| 8243-A-0632-0 | 制造商:AMATOM ELECTRONIC HARDWARE 功能描述: |
| 8243-W | 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類別:靜電控制，ESD，無塵室產(chǎn)品 >> 處理劑，清潔劑，擦拭布 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 處理劑/清潔劑類型:清潔布 使用:電子設(shè)備 技術(shù)規(guī)格:無絨毛，微纖維 數(shù)量:100（12" L x 12" W） 包裝:袋 |
| 8243-W X(25) | 功能描述:化學(xué)物質(zhì) OPTICAL WIPE 25 PER BOX RoHS:否 制造商:3M Electronic Specialty 產(chǎn)品:Adhesives 類型:Epoxy Compound 大小:1.7 oz 外殼:Plastic Tube |
| 8243-WX25 | 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類別:靜電控制，ESD，無塵室產(chǎn)品 >> 處理劑，清潔劑，擦拭布 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 處理劑/清潔劑類型:清潔布 使用:電子設(shè)備 技術(shù)規(guī)格:無絨毛，微纖維 數(shù)量:100（12" L x 12" W） 包裝:袋 |
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