參數(shù)資料
型號： 82439TX
廠商： INTEL CORP
元件分類： 存儲控制器/管理單元
英文描述： System Controller(系統(tǒng)控制器)
中文描述： 256M X 8, DRAM CONTROLLER, PBGA324
封裝： BGA-324
文件頁數(shù)： 54/83頁
文件大?。?/td> 461K
代理商： 82439TX
82439TX (MTXC)
E
54
PRELIMINARY
by the end user; the size and type of DRAM that can be implemented in the 5th row is limited (see the bullets
below).
The total memory supported is 256 MB, even though it is possible to populate the six rows with more than
256 MB. This limit must be ensured by the system BIOS.
EDO/FPM only configuration Requirements
If more than four rows of x4 DRAM devices + one row of x8 DRAM devices of memory is supported, it is
recommended that all six rows be buffered. MA and MWE# enable signals should be buffered. In a system
that only supports x8 or x16 devices (i.e., x4 devices not supported), six rows of memory can be supported
without buffering.
Maximum load supported without buffers: Four rows of x4 DRAM devices + one row of x8 DRAM devices.
A second pair or MA0 and MA1 signals are provided by muxing CKE with MAA0 and CKEB with MAA1. In a
desktop system, it is required that the second pair of MA lines be used to support 5-2-2-2 EDO performance
in more than two rows of memory. The second pair of MA lines are not required in a mobile system,
assuming x4 devices are not used. The MA functionality is selected via DRAMC[bit 2] (67h).
SDRAM only configuration Requirements
Maximum rows supported; Five rows of x8 devices.
SDRAM/EDO/FPM mixing configuration Requirements
If SDRAM and EDO/FPM are mixed in a system, the configuration is limited to a maximum of four rows (two
rows of x4 EDO/FPM and two rows of x8 or x16 SDRAM). If only x8 or x16 EDO/FPM and SDRAM devices
are used (i.e., not x4’s), five rows can be supported.
SDRAMs can be mixed with EDO/FPM on a row by row basis (e.g., row 0 can be populated with SDRAMs
while row 3 is populated with EDO/FPM).
A second pair or MA0 and MA1 signals are provided by muxing CKE with MAA0 and CKEB with MAA1. In a
desktop system, it is required that the second pair of MA lines be used to support 5-2-2-2 EDO performance
in more than two rows of memory. The second pair of MA lines are not required in a mobile system,
assuming x4 devices are not used. The MA functionality is selected via DRAMC[bit 2] (67h).
Table 12 provides a summary of the characteristics of memory configurations supported by the MTXC. Minimum
values listed are obtained with single-sided SIMMs or DIMMs. Maximum values are obtained with double-sided
SIMMs or DIMMs. Note that, for a 64-bit wide memory array, a minimum of two 32-bit wide DRAM SIMMs are
required in any specific row. The minimum values used are also the smallest upgradeable memory size. Please
note that EDO/FPM can also come on x64 DIMM modules.
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相關代理商/技術參數(shù)
參數(shù)描述
82439TXC 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:INTEL 430HX PCISET 82439HX SYSTEM CONTROLLER (TXC)
8243-A-0632-0 制造商:AMATOM ELECTRONIC HARDWARE 功能描述:
8243-W 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類別:靜電控制，ESD，無塵室產(chǎn)品 >> 處理劑，清潔劑，擦拭布 系列:- 標準包裝:100 系列:- 處理劑/清潔劑類型:清潔布 使用:電子設備 技術規(guī)格:無絨毛，微纖維 數(shù)量:100（12" L x 12" W） 包裝:袋
8243-W X(25) 功能描述:化學物質(zhì) OPTICAL WIPE 25 PER BOX RoHS:否 制造商:3M Electronic Specialty 產(chǎn)品:Adhesives 類型:Epoxy Compound 大小:1.7 oz 外殼:Plastic Tube
8243-WX25 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類別:靜電控制，ESD，無塵室產(chǎn)品 >> 處理劑，清潔劑，擦拭布 系列:- 標準包裝:100 系列:- 處理劑/清潔劑類型:清潔布 使用:電子設備 技術規(guī)格:無絨毛，微纖維 數(shù)量:100（12" L x 12" W） 包裝:袋
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