參數(shù)資料
型號: 82439TX
廠商: INTEL CORP
元件分類: 存儲控制器/管理單元
英文描述: System Controller(系統(tǒng)控制器)
中文描述: 256M X 8, DRAM CONTROLLER, PBGA324
封裝: BGA-324
文件頁數(shù): 45/83頁
文件大?。?/td> 461K
代理商: 82439TX
E
3.1.28.
82439TX (MTXC)
45
PRELIMINARY
MCTL
MISCELLANEOUS CONTROL REGISTER
Address Offset:
Default Value:
Access:
79h
00h
Read/Write
Bit
Description
7
Reserved.
6
ACPI Control Register Enable (ACRE)
.
0=Any CPU access to I/O address 0022h is passed on to
the PCI bus. 1=Any CPU access to I/O address 0022h is processed internally in the MTXC. This bit
must be set to 1 before accessing the “Arbiter Disable” bit in the PM2_CNTRL Register (0022h).
5
Suspend Refresh Type (SRT)
.
0=CBR refresh. 1=Self refresh. This bit determines what type of
DRAM refresh is used during Power On Suspend (POS) or Suspend to DRAM modes. This bit
applies to EDO/FPM DRAM only. SDRAM always uses self refresh, regardless of the state of
this bit.
4
Normal Refresh Enable (NREF_EN)
.
Setting this bit to 1 switches MTXC from suspend refresh to
normal refresh. After the reset, this bit must be set by software executing out of EPROM. MTXC
waits for this bit to be set before exiting out of suspend refresh mode.
3
Reserved.
2
Internal Clock Control (Gated Clock) Disable (I
CC
)
.
1=Disable. 0=Enable. This bit, when set to 0,
allows the MTXC to reduce its power consumption (via turning off its internal clocks, to specific
interfaces) when in chip standby mode. This bit defaults to 0.
1:0
Reserved.
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