參數(shù)資料
型號: 82439TX
廠商: INTEL CORP
元件分類: 存儲控制器/管理單元
英文描述: System Controller(系統(tǒng)控制器)
中文描述: 256M X 8, DRAM CONTROLLER, PBGA324
封裝: BGA-324
文件頁數(shù): 70/83頁
文件大小: 461K
代理商: 82439TX
82439TX (MTXC)
E
70
PRELIMINARY
Multi-Transaction Timer (MTT)
The priority chain algorithm has been enhanced by the Multi-Transaction Timer (MTT) mechanism. Once a PCI
agent is granted, the MTT is started. This timer then counts down in PCI clocks from its preset value to zero.
Until the timer expires, that agent will be promoted to being the highest priority PCI agent for the next
grant event.
4.8.2.
CPU POLICIES
The CPU never explicitly requests the bus. Instead, the arbiter grants the bus to the CPU when:
The CPU is the highest priority
PCI agents do not require main memory (peer-to-peer transfers or bus idle) and the PCI bus is not currently
locked by a PCI master
When the CPU is granted as highest priority, the MLT timer is used to guarantee a minimum amount of system
resources to the CPU before another requesting PCI agent is granted.
5.0.
CLOCKS AND RESET
5.1.
Clock Generation and distribution
The MTXC and CPU should be clocked from one clock driver output to minimize skew between the CPU
& MTXC.
5.2.
RESET Sequencing
The MTXC is asynchronously reset when the RST# signal is asserted.
The MTXC arbiter includes support for PCI central resource functions. These functions include driving the
AD[31:0],C/BE[3:0]#, and the PAR signals when no one is granted the PCI bus and the PCI bus is idle. The
MTXC drives 0’s on these signals during these times, plus during RESET.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
82439TXC 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:INTEL 430HX PCISET 82439HX SYSTEM CONTROLLER (TXC)
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