參數(shù)資料
型號(hào): 82439TX
廠商: INTEL CORP
元件分類(lèi): 存儲(chǔ)控制器/管理單元
英文描述: System Controller(系統(tǒng)控制器)
中文描述: 256M X 8, DRAM CONTROLLER, PBGA324
封裝: BGA-324
文件頁(yè)數(shù): 30/83頁(yè)
文件大?。?/td> 461K
代理商: 82439TX
82439TX (MTXC)
E
30
PRELIMINARY
Bit
Description
5
RAS# to CAS# Override (RCO)
.
When set to 1, and the CL bit (CAS Latency) is 0 (CAS
Latency=3), then a RAS# to CAS# delay of 2 HCLKs is provided for SDRAM
.
When set to 0, a RAS#
to CAS# delay for SDRAM is determined by the CL bit
.
4
CAS# Latency (CL).
When set to 1, a CAS# latency of 2 is used for all SDRAM cycles. When reset
to 0, CAS# latency of 3 is used for all SDRAM cycles.
3
RAS# Timing (RT).
This bit controls RAS# precharge, RAS# active to precharge time and Refresh
to RAS# active delay (in HCLKs):
Bit 3
RAS#
RAS# act.
Refresh to
Precharge
to Precharge
RAS# act.
0
3
5
1
3
4
8
7
2
Reserved.
1
64-Mbit Technology Enable (64MTEN).
1=Enable. 0=Disable. When set to 0, the MTXC does not
support 64-Mbit SDRAM devices. In this mode, the MTXC supports 4-Mbit, 16-Mbit, and 64-Mbit
technology for EDO/FPM systems and 4 Mbit and 16 Mbit for SDRAM systems (i.e., 64 Mbit not
supported in SDRAM systems). When set to 1, the MTXC supports 4 Mbit, 16 Mbit, and 64 Mbit
for both SDRAM and EDO/FPM devices. In this mode, the RAS#/CS5# signal becomes
RAS#/CS5#/MA13, RAS4#/CS4# becomes RAS4#/CS4#/BA1, and KRQAK/CS4_64# becomes
CS4_64#. CS4_64# (fifth row) function is provided if this signal is set to 1 and DRAM Cache is not
present in the system (indicated by a 0 in bit 5, register 53h).
0
Reserved.
Table 4 lists the CAS# Latency, RAS# to CAS#, RAS# Precharge, RAS# Active to Precharge and Refresh to
RAS# active programmable timings.
Table 4. Programming Timings
Operating
Frequency
CAS Latency
(CL)
RAS# to
CAS# (Trcd)
RAS#
Precharge
(Trp)
RAS# active
to Precharge
(Tras)
Refresh to
RAS# (Trc)
Register 54h
Bits[5:3]
60/66 MHz
3 HCLKs
3 HCLKs
3 HCLKs
5 HCLKs
8 HCLKs
000
60/66 MHz
3 HCLKs
2 HCLKs
3 HCLKs
5 HCLKs
8 HCLKs
100
60/66 MHz
2 HCLKs
2 HCLKs
3 HCLKs
4 HCLKs
7 HCLKs
011
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