參數(shù)資料
型號: 82439TX
廠商: INTEL CORP
元件分類: 存儲控制器/管理單元
英文描述: System Controller(系統(tǒng)控制器)
中文描述: 256M X 8, DRAM CONTROLLER, PBGA324
封裝: BGA-324
文件頁數(shù): 68/83頁
文件大小: 461K
代理商: 82439TX
82439TX (MTXC)
E
68
PRELIMINARY
4.8.
System Arbitration
The MTXC’s PCI Bus Arbiter allows PCI peer-to-peer traffic concurrent with CPU main memory/second level
cache cycles. The arbiter supports five PCI masters. REQ[3:0]#/GNT[3:0]# are used by PCI masters other than
the PCI-to-ISA expansion bridge (PIIX4). PHLD#/PHLDA# are the arbitration request/grant signals for the PIIX4
and provide guaranteed access time capability for ISA masters. PHLD#/PHLDA# also optimize system
performance based on the PIIX4 known policies.
Arbiter
PHLD#
REQ0#
REQ1#
REQ2#
REQ3#
PHLDA#
GNT0#
GNT1#
GNT2#
GNT3#
mtxc_06
Figure 10. PCI Arbiter
4.8.1.
PRIORITY SCHEME AND BUS GRANT
The highest priority requester is determined by a fixed order queue together with a highest priority pointer.
Although the priority ring is fixed, the highest priority pointer moves to determine which PCI agent is at the top
(and bottom) of the queue. The arbiter counts three grant assertions to requesters different than the one it is
currently granting (and all grants within MTT are collapsed to one) to decide when it’s time to let the host in.
The grant signals (GNTx#) are normally negated after recognition of FRAME# assertion, or 16 PCLKs from grant
assertion, if no cycle has started.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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