- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378215 > 82439TX (INTEL CORP) System Controller(系統(tǒng)控制器) PDF資料下載
參數(shù)資料
| 型號： | 82439TX |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | System Controller(系統(tǒng)控制器) |
| 中文描述： | 256M X 8, DRAM CONTROLLER, PBGA324 |
| 封裝： | BGA-324 |
| 文件頁數(shù)： | 67/83頁 |
| 文件大?。?/td> | 461K |
| 代理商： | 82439TX |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁當(dāng)前第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁
E
4.7.
82439TX (MTXC)
67
PRELIMINARY
PCI Interface
The MTXC integrates a high performance interface to the PCI local bus taking full advantage of the high
bandwidth and low latency of PCI. The MTXC is fully PCI 2.1 compliant. Table 22 lists the PCI bus commands
supported. Five PCI masters are supported by the integrated arbiter including the PIIX4 and four general PCI
masters. The MTXC acts as a PCI master for CPU accesses to PCI. The PCI bus is clocked at one half the
frequency of the CPU clock. This divided synchronous interface minimizes latency for CPU-to-PCI cycles and
PCI-to-main memory cycles.
The MTXC integrates posted write buffers for CPU memory writes to PCI. Back-to-back sequential memory
writes to PCI are converted to burst writes on PCI. This feature allows the CPU to continue posting DWord
writes at the maximum bandwidth for the Pentium processor for the highest possible transfer rates to the
graphics frame buffer.
Read prefetch and write posting buffers in the MTXC enable PCI masters to access main memory at up to
120 MB/sec. The MTXC incorporates a snoop ahead feature that allows PCI masters to continue bursting on
both reads and writes even as the bursts cross cache line boundaries.
The MTXC forwards each of the CPU shutdown, Halt, and Stop Grant cycles to the PCI bus as special cycles.
These cycles are terminated on PCI as master abort and a BRDY# is returned to the CPU. The Stop Grant cycle
is propagated with 0002h in the message field and 0012h in the message dependent data field.
Table 22. PCI Commands
C/BE#
Command
Target Support
Initiator Support
0000
Interrupt Acknowledge
NO
YES
0001
Special cycle
NO
YES
0010
I/O read
YES
YES
0011
I/O write
YES
YES
0100
reserved
NO
NO
0101
reserved
NO
NO
0110
Memory read
YES
YES
0111
Memory write
YES
YES
1000
reserved
NO
NO
1001
reserved
NO
NO
1010
Configuration Read
NO
YES
1011
Configuration Write
NO
YES
1100
Memory Read Multiple
As Memory Read
NO
1101
Dual Address Cycle
NO
NO
1110
Memory Read Line
As Memory Read
NO
1111
Memory Write and Invalidate
As Memory Write
NO
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 82443MX | PCIset |
| 82443ZX | Intel㈢ 440ZX AGPset: Host Bridge/Controller |
| 82451NX | Intel 450NX PCIset |
| 82452NX | Intel 450NX PCIset |
| 82453NX | Intel 450NX PCIset |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82439TXC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:INTEL 430HX PCISET 82439HX SYSTEM CONTROLLER (TXC) |
| 8243-A-0632-0 | 制造商:AMATOM ELECTRONIC HARDWARE 功能描述: |
| 8243-W | 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類別:靜電控制，ESD，無塵室產(chǎn)品 >> 處理劑，清潔劑，擦拭布 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 處理劑/清潔劑類型:清潔布 使用:電子設(shè)備 技術(shù)規(guī)格:無絨毛，微纖維 數(shù)量:100（12" L x 12" W） 包裝:袋 |
| 8243-W X(25) | 功能描述:化學(xué)物質(zhì) OPTICAL WIPE 25 PER BOX RoHS:否 制造商:3M Electronic Specialty 產(chǎn)品:Adhesives 類型:Epoxy Compound 大小:1.7 oz 外殼:Plastic Tube |
| 8243-WX25 | 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類別:靜電控制，ESD，無塵室產(chǎn)品 >> 處理劑，清潔劑，擦拭布 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 處理劑/清潔劑類型:清潔布 使用:電子設(shè)備 技術(shù)規(guī)格:無絨毛，微纖維 數(shù)量:100（12" L x 12" W） 包裝:袋 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。