參數(shù)資料
型號(hào)： 82439TX
廠商： INTEL CORP
元件分類： 存儲(chǔ)控制器/管理單元
英文描述： System Controller(系統(tǒng)控制器)
中文描述： 256M X 8, DRAM CONTROLLER, PBGA324
封裝： BGA-324
文件頁(yè)數(shù)： 6/83頁(yè)
文件大?。?/td> 461K
代理商： 82439TX
82439TX (MTXC)
E
6
PRELIMINARY
1.0.
ARCHITECTURE OVERVIEW
The MTXC host bridge provides a completely integrated solution for the system controller and datapath
components in a Pentium processor system. The MTXC Supports all Pentium family processors since P54C, it
has 64-bit Host and DRAM Bus Interface, 32-bit PCI Bus Interface, Second level Cache Interface, and it
integrates the PCI arbiter.
The MTXC interfaces with the Pentium processor host bus, a dedicated memory data bus, and the PCI bus
(see Figure 1).
The MTXC bus interfaces are designed to interface with 2.5V, 3.3V and 5V busses. The MTXC implements 2.5V
and 3.3V drivers and 5V tolerant receivers. The MTXC connects directly to the Pentium processor 3.3V or 2.5V
host bus, directly to 5V or 3.3V DRAMs, and directly to the 5V or 3.3V PCI bus. The 430TX also interfaces
directly to the 3.3V or 5.0V TAGRAM and 3.3V Cache.
The MTXC works with the PCI IDE/ISA Accelerator 4 (PIIX4). The PIIX4 provides the PCI-to-ISA/EIO bridge
functions along with other features such as a fast IDE interface (PIO mode 4 and Ultra DMA/33), Plug-n-Play
port, APIC interface, PCI 2.1 Compliance, SMBUS interface, and Universal Serial Bus Host Controller functions.
DRAM Interface
The DRAM interface is a 64-bit data path that supports Standard (or Fast) Page Mode (FPM), Extended Data
Out (EDO) and Synchronous DRAM (SDRAM) memory. The DRAM controller inside the MTXC is capable of
generating 3-1-1-1 for posted writes for any type of DRAM that is used. While read performance is 6-1-1-1 for
SDRAM, 5-2-2-2 for EDO, and 6-3-3-3 for FPM.
The DRAM interface supports 4 Mbytes to 256 Mbytes with six RAS lines. The MTXC supports 4-Mbit, 16-Mbit,
and 64-Mbit DRAM and SDRAM technology, both symmetrical and asymmetrical. Parity is not supported, and
for loading reasons, x32 and x64 SIMMs/DIMMs/SO-DIMMs should be used.
Second Level Cache
The second level cache is direct mapped and supports both 256-Kbyte and 512-Kbyte SRAM configuration
using Pipeline Burst SRAM or DRAM Cache SRAM. The Cache performance is 3-1-1-1 for line read/write and
3-1-1-1-1-1-1-1 for back to back reads that are pipelined. Cacheless configuration is also supported.
PCI Interface
The PCI interface is 2.1 compliant and supports up to four PCI bus masters in addition to the PIIX4 bus master
requests.
Datapath and Buffers
The MTXC contains three sets of data buffers for optimizing data flow. A five QWord deep DRAM write buffer is
provided for CPU-to-DRAM writes, second level cache write backs, and PCI-to-DRAM transfers. This buffer is
used to achieve 3-1-1-1 posted writes to DRAM and also provides DWord merging and burst merging for CPU-
to-DRAM write cycles. In addition, an extra line of buffering is provided that is combined with the DRAM Write
Buffer to supply an 18 DWord deep buffer for PCI to main memory writes. A five DWord buffer is provided for
CPU-to-PCI writes to help maximize the bandwidth for graphic writes to the PCI bus. Also, five QWords of
prefetch buffering has been added to the PCI-to-DRAM read path that allows up to two lines of data to be
prefetched at an x-2-2-2 rate. The MTXC interfaces directly to the Host and DRAM data bus.
Power Management Features
The MTXC implements extensive power management features. The CLKRUN# feature enables controlling of the
PCI clock (on/off). The MTXC supports POS, STR, STD, and Soft-off suspend states. SUSCLK and
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
82439TXC 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:INTEL 430HX PCISET 82439HX SYSTEM CONTROLLER (TXC)
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8243-WX25 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類別:靜電控制，ESD，無(wú)塵室產(chǎn)品 >> 處理劑，清潔劑，擦拭布 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 處理劑/清潔劑類型:清潔布 使用:電子設(shè)備 技術(shù)規(guī)格:無(wú)絨毛，微纖維 數(shù)量:100（12" L x 12" W） 包裝:袋
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