- 您現在的位置：買賣IC網 > PDF目錄378215 > 82439TX (INTEL CORP) System Controller(系統(tǒng)控制器) PDF資料下載
參數資料
| 型號： | 82439TX |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | System Controller(系統(tǒng)控制器) |
| 中文描述： | 256M X 8, DRAM CONTROLLER, PBGA324 |
| 封裝： | BGA-324 |
| 文件頁數： | 57/83頁 |
| 文件大?。?/td> | 461K |
| 代理商： | 82439TX |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁當前第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁
E
4.3.3.
82439TX (MTXC)
57
PRELIMINARY
DRAM ADDRESS TRANSLATION
The multiplexed row/column address to the DRAM memory array is provided by the MA[11:0] signals (MA[13:0]
for SDRAM 64-Mbit support). The MA bits are derived from the host or PCI address bus as defined by the
Table 14. The MTXC supports a 2K byte page size only. The MA lines are translated from the address lines
A[26:3] for all memory accesses.
Table 14. MTXC DRAM Address Map Summary
ADDR
MA13
MA12/
BA1
MA11/
BA0
MA10
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
Row
A24
A23
A11
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
Col
A23
A26/
A11
A11/
A25
“V”
A11/
A24/
A26
A11/
A22/
A23/
A25
A10
A9
A8
A7
A6
A5
A4
A3
NOTES:
1.
V=Valid level (either 0 or 1) used for SDRAMs. It is 1 during the initialization sequence. It is 0 during normal
mode of operation.
2.
BA0 and BA1 are the muxed bank selects for SDRAM. Bank select BA1 is required for 64-Mbit SDRAM
support.
4.3.4.
DRAM PAGING
If DRAMC[bit 4]=1, the MTXC keeps the page open until a page or row miss occurs. If DRAMC[bit 4]=0 (default),
the DRAM page is kept open when:
CPU host bus is non-idle, or
PCI interface owns the bus.
4.3.5.
DRAM TYPES
4.3.5.1.
FPM Mode
The MTXC, as a default, supports the standard fast page mode (FPM) DRAM.
4.3.5.2.
EDO Mode
Extended Data Out (or Hyper Page Mode) DRAM is designed to improve the DRAM read performance. EDO
DRAM holds the memory data valid until the next CAS# falling edge. Compared to standard page mode DRAM
which tri-states the memory data when CAS# negates to precharge. With EDO, the CAS# precharge overlaps
the memory data valid time. This allows CAS# to negate earlier while still satisfying the memory data valid
window time.
4.3.5.3.
SDRAM Mode
Synchronous DRAM (SDRAM) implements a fully synchronous interface as compared to a conventional DRAM
whose timing delays are related to the rising and falling edges of the RAS#, CAS#, and WE# input signals. The
430TX supports all of the features and timings as shown in the “SDRAM PC” specification. The objective of the
SDRAM
PC Specification is to enable low cost and easily manufactureable SDRAMs for the main stream volume
相關PDF資料 |
PDF描述 |
|---|---|
| 82443MX | PCIset |
| 82443ZX | Intel㈢ 440ZX AGPset: Host Bridge/Controller |
| 82451NX | Intel 450NX PCIset |
| 82452NX | Intel 450NX PCIset |
| 82453NX | Intel 450NX PCIset |
相關代理商/技術參數 |
參數描述 |
|---|---|
| 82439TXC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:INTEL 430HX PCISET 82439HX SYSTEM CONTROLLER (TXC) |
| 8243-A-0632-0 | 制造商:AMATOM ELECTRONIC HARDWARE 功能描述: |
| 8243-W | 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類別:靜電控制，ESD，無塵室產品 >> 處理劑，清潔劑，擦拭布 系列:- 標準包裝:100 系列:- 處理劑/清潔劑類型:清潔布 使用:電子設備 技術規(guī)格:無絨毛，微纖維 數量:100（12" L x 12" W） 包裝:袋 |
| 8243-W X(25) | 功能描述:化學物質 OPTICAL WIPE 25 PER BOX RoHS:否 制造商:3M Electronic Specialty 產品:Adhesives 類型:Epoxy Compound 大小:1.7 oz 外殼:Plastic Tube |
| 8243-WX25 | 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類別:靜電控制，ESD，無塵室產品 >> 處理劑，清潔劑，擦拭布 系列:- 標準包裝:100 系列:- 處理劑/清潔劑類型:清潔布 使用:電子設備 技術規(guī)格:無絨毛，微纖維 數量:100（12" L x 12" W） 包裝:袋 |
發(fā)布緊急采購，3分鐘左右您將得到回復。