參數(shù)資料
型號: 82439TX
廠商: INTEL CORP
元件分類: 存儲控制器/管理單元
英文描述: System Controller(系統(tǒng)控制器)
中文描述: 256M X 8, DRAM CONTROLLER, PBGA324
封裝: BGA-324
文件頁數(shù): 11/83頁
文件大小: 461K
代理商: 82439TX
E
82439TX (MTXC)
11
PRELIMINARY
Name
Type
Description
CKEB/MAA1
O
3.3 V
SDRAM Clock Enable (SDRAM) (second copy).
SDRAM
clock enable pin. When
this signal is negated, SDRAM enters into power down mode. Note that this signal
is not implemented in the “Suspend Well” and should not be used if suspend to
RAM (STR) is implemented. This signal is also muxed to provide a second copy of
memory address MA1 (MAA1). The MA function is selected via DRT[bit2] (offset
67h).
MTXC negates CKE (and CKEB) when SUSSTAT1# is asserted. Note that MTXC
asserts CKE (and CKEB) for all rows (i.e., CKE and CKEB cannot be selectively
asserted for certain rows and negated for other rows).
MD[63:0]
I/O
3.3V/5V
Memory Data.
These signals are connected to the DRAM data bus. These signals
have internal pull-down resistors
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