參數(shù)資料
型號(hào)： 82439TX
廠(chǎng)商： INTEL CORP
元件分類(lèi)： 存儲(chǔ)控制器/管理單元
英文描述： System Controller(系統(tǒng)控制器)
中文描述： 256M X 8, DRAM CONTROLLER, PBGA324
封裝： BGA-324
文件頁(yè)數(shù)： 8/83頁(yè)
文件大?。?/td> 461K
代理商： 82439TX
82439TX (MTXC)
E
8
PRELIMINARY
2.0.
SIGNAL DESCRIPTION
This section provides a detailed description of each signal. The signals are arranged in functional groups
according to their associated interface.
The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is
at a low voltage level. When “#” is not present after the signal name, the signal is asserted when at the high
voltage level.
The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a
mixture of “active low” and “active high” signal. The term assert, or assertion indicates that a signal is active,
independent of whether that level is represented by a high or low voltage. The term negate, or negation indicates
that a signal is inactive.
The I/O buffer types are shown below:
Buffer Type
I
O
I/O
s/t/s
od
3.3V/2.5V
Description
input only signal
totem pole output
bi-direction, tri-state input/output pin
sustained tri-state
open drain
Indicates the buffer is 3.3V or 2.5V only, depending on the voltage (3.3V or 2.5V) connected to
VccX pins.
Indicates that the output is 3.3V and input is 3.3V receiver with 5V tolerance.
Indicates 3.3V receiver with 5V tolerance.
3.3V/5V
5V
2.1.
MTXC Signals
2.1.1.
HOST INTERFACE
Name
Type
Description
A[31:3]
I/O
3.3V/2.5V
Address Bus.
A[31:3] connects to the address bus of the CPU. During CPU
cycles A[31:3] are inputs. The MTXC drives A[31:3] during inquire cycles on
behalf of PCI initiators. Bits A[31:26] act as inputs when RST# is active
BE[7:0]#
I
3.3V/2.5V
Byte Enables.
The CPU byte enables indicate which byte lane the current CPU
cycle is accessing. All eight byte lanes must be provided to the CPU if the cycle
is a cacheable read regardless of the state of BE[7:0]#.
ADS#
I
3.3V/2.5V
Address Status.
CPU asserts ADS# in T1 of the CPU bus cycle.
BRDY#
O
3.3V/2.5V
Bus Ready.
The MTXC asserts BRDY# to indicate to the CPU that data is
available on reads or has been received on writes.
NA#
O
3.3V/2.5V
Next Address.
This signal is asserted by the MTXC to indicate to the Processor
that it is ready to process a second cycle.
相關(guān)PDF資料
PDF描述
82443MX PCIset
82443ZX Intel㈢ 440ZX AGPset: Host Bridge/Controller
82451NX Intel 450NX PCIset
82452NX Intel 450NX PCIset
82453NX Intel 450NX PCIset
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
82439TXC 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:INTEL 430HX PCISET 82439HX SYSTEM CONTROLLER (TXC)
8243-A-0632-0 制造商:AMATOM ELECTRONIC HARDWARE 功能描述:
8243-W 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類(lèi)別:靜電控制，ESD，無(wú)塵室產(chǎn)品 >> 處理劑，清潔劑，擦拭布 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 處理劑/清潔劑類(lèi)型:清潔布 使用:電子設(shè)備 技術(shù)規(guī)格:無(wú)絨毛，微纖維 數(shù)量:100（12" L x 12" W） 包裝:袋
8243-W X(25) 功能描述:化學(xué)物質(zhì) OPTICAL WIPE 25 PER BOX RoHS:否 制造商:3M Electronic Specialty 產(chǎn)品:Adhesives 類(lèi)型:Epoxy Compound 大小:1.7 oz 外殼:Plastic Tube
8243-WX25 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類(lèi)別:靜電控制，ESD，無(wú)塵室產(chǎn)品 >> 處理劑，清潔劑，擦拭布 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 處理劑/清潔劑類(lèi)型:清潔布 使用:電子設(shè)備 技術(shù)規(guī)格:無(wú)絨毛，微纖維 數(shù)量:100（12" L x 12" W） 包裝:袋
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*