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參數(shù)資料
| 型號： | 82439TX |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | System Controller(系統(tǒng)控制器) |
| 中文描述： | 256M X 8, DRAM CONTROLLER, PBGA324 |
| 封裝： | BGA-324 |
| 文件頁數(shù)： | 65/83頁 |
| 文件大?。?/td> | 461K |
| 代理商： | 82439TX |
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The 430TX system maintains a very low power CPU complex by utilizing the different power down features
available from the CPU, cache data RAMs and utilizing leading edge low power design techniques in the 430TX
system components. The 430TX components work in unison to dynamically control the CPU complexes power
state without adversely affecting performance. The following gives a brief description of how the 430TX system
components achieve these low power states.
82439TX (MTXC)
65
PRELIMINARY
The MTXC and PIIX4 work in unison to maintain a very low power L2 subsystem without adversely affecting
peak performance.
NOTE
There are some system restrictions when DRAM Cache is implemented in a system that supports
STP_CLK, POS, and STR power management modes. Since KRQAK is not implemented in the
“Suspend Well,” the correct operation of KRQAK is not guaranteed when the system enters the above
mentioned power management modes. To avoid data corruption in the L2 cache, a system that
implements the STP_CLK, POS, and STR modes must abide by the following rules:
1. Before entering these power management modes, the DRAM cache must be flushed so that all
modified lines end up in system memory.
2. After exiting these power management modes, the DRAM Cache must be reinitialized.
4.6.1.
CHIP STANDBY
The MTXC also supports a chip standby mode. When the MTXC determines that both its CPU interface and PCI
interface are idle, it will dynamically place itself into a very low power state. While in chip standby state the
MTXC is able to respond to new CPU or PCI bus master accesses with no performance penalty. This provides
very optimized power/performance characteristics because the CPU interface are idle for large periods of time.
The MTXC enters Chip Standby mode when the following conditions are true:
Host Bus idle
PCI bus Idle
Normal Mode (i.e., not Test Mode)
Not in RESET state
Internal operations idle
Entering the Chip Standby state is not dependent on any timer expiration. When the above conditions are met,
the MTXC can enter the chip standby state as soon as it can.
4.6.2.
SUSPEND/RESUME
The MTXC supports POS, STR, STD and SOFF (Soft Off) suspend states. The MTXC supports the POS mode
by maintaining all of its power planes when in the suspend state. The MTXC supports the STR modes by
isolating its CPU and PCI interfaces, and only maintaining the DRAM refresh off the SUSCLK signal. When
exiting the STR modes, the MTXC’s core well is reset and its context is lost (the power management context is
not lost however). The MTXC supports the STD and SOFF modes by being totally powered off.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 82443MX | PCIset |
| 82443ZX | Intel㈢ 440ZX AGPset: Host Bridge/Controller |
| 82451NX | Intel 450NX PCIset |
| 82452NX | Intel 450NX PCIset |
| 82453NX | Intel 450NX PCIset |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82439TXC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:INTEL 430HX PCISET 82439HX SYSTEM CONTROLLER (TXC) |
| 8243-A-0632-0 | 制造商:AMATOM ELECTRONIC HARDWARE 功能描述: |
| 8243-W | 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類別:靜電控制，ESD，無塵室產(chǎn)品 >> 處理劑，清潔劑，擦拭布 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 處理劑/清潔劑類型:清潔布 使用:電子設(shè)備 技術(shù)規(guī)格:無絨毛，微纖維 數(shù)量:100（12" L x 12" W） 包裝:袋 |
| 8243-W X(25) | 功能描述:化學(xué)物質(zhì) OPTICAL WIPE 25 PER BOX RoHS:否 制造商:3M Electronic Specialty 產(chǎn)品:Adhesives 類型:Epoxy Compound 大小:1.7 oz 外殼:Plastic Tube |
| 8243-WX25 | 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類別:靜電控制，ESD，無塵室產(chǎn)品 >> 處理劑，清潔劑，擦拭布 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 處理劑/清潔劑類型:清潔布 使用:電子設(shè)備 技術(shù)規(guī)格:無絨毛，微纖維 數(shù)量:100（12" L x 12" W） 包裝:袋 |
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