參數(shù)資料
型號: 82439TX
廠商: INTEL CORP
元件分類: 存儲控制器/管理單元
英文描述: System Controller(系統(tǒng)控制器)
中文描述: 256M X 8, DRAM CONTROLLER, PBGA324
封裝: BGA-324
文件頁數(shù): 41/83頁
文件大?。?/td> 461K
代理商: 82439TX
E
3.1.24.
82439TX (MTXC)
41
PRELIMINARY
DRTL—DRAM ROW TYPE REGISTER LOW
Address Offset:
Default Value:
Access:
68h
00h
Read/Write
This 8-bit register identifies the type of DRAM (EDO, SPM (standard page mode)), or SDRAM (synchronous
DRAM) used in rows 0 to 3 and should be programmed by BIOS for optimum performance if EDO DRAM’s or
SDRAMs are used. The hardware uses these bits to determine the correct cycle timing to use before a DRAM
cycle is run.
Bit
Description
7:0
DRAM Row Type (DRT).
The DRT bits select the DRAM type installed in each physical DRAM
Row. Each one-of-four bit pairs in this register corresponds to the DRAM row identified by the
corresponding DRB register.
DRT Bits
7,3
6,2
5,1
4,0
DRAM Row
3
2
1
0
DRT
0,0
0,1
1,0
1,1
DRAM Type value definitions
SPM DRAM
EDO DRAM
SDRAM
reserved
3.1.25.
MTT
MULTI-TRANSACTION TIMER REGISTER (RESERVED TEST MODE REGISTER)
Address Offset:
Default Value:
Access:
70h
20h
Read/Write
MTT is an 8-bit register that controls the amount of time that the MTXC’s arbiter allows a PCI initiator to perform
multiple transactions on the PCI bus. The MTT guarantees the minimum time, measured in PCLKs, that the PCI
agent retains the ownership of the PCI bus from the initial assertion of grant.
Bit
Description
7:2
MTT Count value.
The number of clocks programmed in the MTT represents the guaranteed time
slice (in PCLKs) allotted to the current agent, after which the MTXC will grant the bus as soon as
another PCI agent requests the bus. The value of 00h disables this function. The count value should
be set to multiples of 4 (i.e., 2 lsbs are ignored).
1:0
Reserved.
Hardwired to 0. (i.e., counter has a resolution of 4 PCLKs)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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