參數(shù)資料
型號: 82439TX
廠商: INTEL CORP
元件分類: 存儲控制器/管理單元
英文描述: System Controller(系統(tǒng)控制器)
中文描述: 256M X 8, DRAM CONTROLLER, PBGA324
封裝: BGA-324
文件頁數(shù): 23/83頁
文件大?。?/td> 461K
代理商: 82439TX
E
3.1.4.
82439TX (MTXC)
23
PRELIMINARY
VID
VENDOR IDENTIFICATION REGISTER
Address Offset:
Default Value:
Attribute:
00–01h
8086h
Read Only
The VID Register contains the vendor identification number. This 16-bit register combined with the Device
Identification Register uniquely identify any PCI device. Writes to this register have no effect.
Bit
Description
15:0
Vendor Identification Number
.
This is a 16-bit value assigned to Intel.
3.1.5.
DID
DEVICE IDENTIFICATION REGISTER
Address Offset:
Default Value:
Attribute:
02–03h
7100h
Read Only
This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI device. Writes to
this register have no effect.
Bit
Description
15:0
Device Identification Number
.
This is a 16 bit value assigned to the MTXC.
3.1.6.
PCICMD
PCI COMMAND REGISTER
Address Offset:
Default:
Access:
04–05h
06h
Read/Write
This 16-bit register provides basic control over the MTXC’s ability to respond to PCI cycles. The PCICMD
Register in the MTXC enables and disables the assertion of SERR# and PCI master accesses to main memory.
Bit
Description
15:10
Reserved
.
9
Fast Back-to-Back (FB2B). (Not implemented)
This bit is hardwired to 0.
8
SERR# Enable (SERRE)
.
(Not implemented)
This bit is hardwired to 0.
7
Address/Data Stepping
.
(Not implemented)
This bit is hardwired to 0.
6
Parity Error Enable (PERRE)
.
(Not implemented)
This bit is hardwired to 0.
5
Video Pallet Snooping (VPS)
.
(Not implemented)
This bit is hardwired to 0.
4
Memory Write and Invalidate Enable (MWIE)
.
(Not implemented)
This bit is hardwired to 0. The
MTXC will never use the Memory Write and Invalidate PCI command.
3
Special Cycle Enable (SCE)
.
(Not implemented)
This bit is hardwired to 0, as the MTXC does not
respond to PCI special cycles.
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