- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378215 > 82439TX (INTEL CORP) System Controller(系統(tǒng)控制器) PDF資料下載
參數(shù)資料
| 型號： | 82439TX |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | System Controller(系統(tǒng)控制器) |
| 中文描述： | 256M X 8, DRAM CONTROLLER, PBGA324 |
| 封裝： | BGA-324 |
| 文件頁數(shù)： | 49/83頁 |
| 文件大?。?/td> | 461K |
| 代理商： | 82439TX |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁當(dāng)前第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁
E
4.2.1.
82439TX (MTXC)
49
PRELIMINARY
CLOCK LATENCIES
Table 11 lists the latencies for various processor transfers to and from the second level cache.
Table 11. Second Level Cache Latencies with Pipelined Burst SRAM
Cycle Type
HCLK Count
Burst Read
3-1-1-1
Burst Write (write back)
3-1-1-1
Single Read
3
Single Write
3
Pipelined Back-to-Back Burst Reads
3-1-1-1,1-1-1-1 (note 1)
NOTES:
1.
The back to back cycles do not account for CPU idle clocks between cycles.
4.2.2.
SNOOP CYCLES
The snoop (or inquire) cycle is used to probe the first level and second level caches when a PCI master
attempts to access main memory. This is done in order to maintain coherency between the first and second level
caches and main memory.
To maintain optimum PCI bandwidth to DRAM, the MTXC utilizes a snoop ahead algorithm. Once the snoop for
the first cache line of a transfer has completed, the MTXC automatically snoops the next sequential cache line.
This algorithm enables the MTXC to continue burst transfers across cache line boundaries.
Reads
Snoop cycles are performed by driving the PCI master address onto the host address bus and asserting
EADS#. The processor then performs a tag lookup to determine whether the addressed memory is in the first
level cache. If the snoop hit is to a Modified Line in the first level cache (HITM# asserted), then the line in the first
level cache is posted to the DRAM Posted Write buffers. The line in the second level cache (if it exists) is
invalidated. The line in the first level cache is not invalidated if the INV pin on the CPU is tied to the KEN# signal
from the MTXC. KEN#/INV will be driven low by the MTXC with EADS# assertion during PCI master
read cycles.
At the same time as the first level snoop cycle, the MTXC performs a tag lookup to determine whether the
addressed memory is in the second level cache. A hit to a modified line in the second level cache also results in
a writeback to DRAM posted write buffers if HITM# is not asserted. The PCI data is serviced from the DRAM
after the line has been retired to DRAM.
Writes
PCI Master write cycles never result in a write directly into the second level cache. A snoop hit to a modified line
in either the first or second caches results in a writeback of that line to main memory. If both the first and second
level caches have modified lines, then the line is written back from the first level cache. In all cases lines in the
first and second level caches are invalidated and the PCI write to main memory occurs after the writeback
completes. A PCI master write snoop hit to an unmodified line in either the first or second level caches results in
the line being invalidated. KEN#/INV will be driven high by the MTXC with EADS# assertion during PCI master
write cycles.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 82443MX | PCIset |
| 82443ZX | Intel㈢ 440ZX AGPset: Host Bridge/Controller |
| 82451NX | Intel 450NX PCIset |
| 82452NX | Intel 450NX PCIset |
| 82453NX | Intel 450NX PCIset |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82439TXC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:INTEL 430HX PCISET 82439HX SYSTEM CONTROLLER (TXC) |
| 8243-A-0632-0 | 制造商:AMATOM ELECTRONIC HARDWARE 功能描述: |
| 8243-W | 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類別:靜電控制，ESD，無塵室產(chǎn)品 >> 處理劑，清潔劑，擦拭布 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 處理劑/清潔劑類型:清潔布 使用:電子設(shè)備 技術(shù)規(guī)格:無絨毛，微纖維 數(shù)量:100（12" L x 12" W） 包裝:袋 |
| 8243-W X(25) | 功能描述:化學(xué)物質(zhì) OPTICAL WIPE 25 PER BOX RoHS:否 制造商:3M Electronic Specialty 產(chǎn)品:Adhesives 類型:Epoxy Compound 大小:1.7 oz 外殼:Plastic Tube |
| 8243-WX25 | 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類別:靜電控制，ESD，無塵室產(chǎn)品 >> 處理劑，清潔劑，擦拭布 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 處理劑/清潔劑類型:清潔布 使用:電子設(shè)備 技術(shù)規(guī)格:無絨毛，微纖維 數(shù)量:100（12" L x 12" W） 包裝:袋 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。