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參數(shù)資料
| 型號(hào)： | 82439TX |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲(chǔ)控制器/管理單元 |
| 英文描述： | System Controller(系統(tǒng)控制器) |
| 中文描述： | 256M X 8, DRAM CONTROLLER, PBGA324 |
| 封裝： | BGA-324 |
| 文件頁數(shù)： | 51/83頁 |
| 文件大?。?/td> | 461K |
| 代理商： | 82439TX |
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Seven Programmable Attribute Map (PAM) Registers are used to specify the cacheability, PCI enable, and
read/write status of the memory space between 640 Kbytes and 1 Mbytes. Each PAM Register defines a
specific address area enabling the system to selectively mark specific memory ranges as cacheable, read only,
write only, read/write, or disabled. When a memory range is disabled, all CPU accesses to that range are
forwarded to PCI.
82439TX (MTXC)
51
PRELIMINARY
The MTXC also supports one of two memory holes, either from 512 KB–640 KB or from 14/15 MB–16 MB in
main memory. Accesses to the memory holes are forwarded to PCI. The memory hole can be enabled/disabled
through the DRAM Control register. All other memory from 1M to 256 MB is read/write L1 cacheable, and is L2
cacheable up to 64 MB.
An optional Extended SMRAM DRAM memory space is also supported in the 256-MB to 512-MB address range.
It consists of the 640-KB–1-MB DRAM area aliased at the 256-MB memory segment, and also an optional
128K/256K/512K/1M DRAM area chopped from the Top-of-DRAM memory and aliased above 256 MB in a
similar manner.
4.3.1.
DRAM ORGANIZATION
The MTXC integrates a DRAM controller that supports EDO, FPM, and SDRAM. SDRAM, EDO and FPM
DRAM’s can be mixed between rows, however, a given row must contain only one type of DRAM. When DRAM
types are mixed (EDO, FPM and SDRAM) each row will run optimized for that particular type of DRAM.
The MTXC supports six rows of memory (six RAS#/CS# lines). For maximum memory flexibility and
performance, it is recommended that a DRAM configuration of four rows be used. This allows 64-Mbit DRAM
devices to be used as well as the mixing of SDRAM and EDO/FPM. Figure 6 shows an EDO/FPM configuration
using x32 SIMM modules and Figure 7 shows a four row EDO/FPM/SDRAM configuration using x64 DIMM
modules (or x64 SO-DIMM).
NOTE
It is not recommended to mix SDRAM (which are 3V devices) with 5V EDO/FPM SIMMs, unless the
SDRAM and EDO/FPM are properly isolated (e.g., isolate the memory data lines with Qswitches). Mixing
5V and 3V memory is not recommend for reliability reasons. Not all SDRAMs are 5V tolerant.
相關(guān)PDF資料 |
PDF描述 |
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| 82443MX | PCIset |
| 82443ZX | Intel㈢ 440ZX AGPset: Host Bridge/Controller |
| 82451NX | Intel 450NX PCIset |
| 82452NX | Intel 450NX PCIset |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82439TXC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:INTEL 430HX PCISET 82439HX SYSTEM CONTROLLER (TXC) |
| 8243-A-0632-0 | 制造商:AMATOM ELECTRONIC HARDWARE 功能描述: |
| 8243-W | 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類別:靜電控制，ESD，無塵室產(chǎn)品 >> 處理劑，清潔劑，擦拭布 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 處理劑/清潔劑類型:清潔布 使用:電子設(shè)備 技術(shù)規(guī)格:無絨毛，微纖維 數(shù)量:100（12" L x 12" W） 包裝:袋 |
| 8243-W X(25) | 功能描述:化學(xué)物質(zhì) OPTICAL WIPE 25 PER BOX RoHS:否 制造商:3M Electronic Specialty 產(chǎn)品:Adhesives 類型:Epoxy Compound 大小:1.7 oz 外殼:Plastic Tube |
| 8243-WX25 | 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類別:靜電控制，ESD，無塵室產(chǎn)品 >> 處理劑，清潔劑，擦拭布 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 處理劑/清潔劑類型:清潔布 使用:電子設(shè)備 技術(shù)規(guī)格:無絨毛，微纖維 數(shù)量:100（12" L x 12" W） 包裝:袋 |
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