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參數(shù)資料
| 型號： | 82439TX |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | System Controller(系統(tǒng)控制器) |
| 中文描述： | 256M X 8, DRAM CONTROLLER, PBGA324 |
| 封裝： | BGA-324 |
| 文件頁數(shù)： | 26/83頁 |
| 文件大小： | 461K |
| 代理商： | 82439TX |
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82439TX (MTXC)
E
26
PRELIMINARY
3.1.11.
HEDT
HEADER TYPE REGISTER
Address Offset:
Default Value:
Access:
0Eh
00h
Read Only
This register contains the Header Type of the MTXC. This code is 00h indicating that the MTXC’s configuration
space map follows the basic format.
Bit
Description
7:0
Device Type (DEVICET).
00h=Indicates a basic configuration space format.
3.1.12.
BIST
BIST REGISTER
Address Offset:
Default Value:
Access:
0Fh
00h
Read/Write
The Built In Self Test (BIST) function is not supported by the MTXC. Writes to this register have no effect.
Bit
Description
7
BIST Supported
.
This read only bit is always set to 0, disabling the BIST function. Writes to this bit
position have no effect.
Start BIST
.
This function is not supported and writes have no effect.
Reserved
.
Completion Code
.
This read only field always returns 0 when read and writes have no effect.
6
5:4
3:0
3.1.13.
ACON
ARBITRATION CONTROL REGISTER
Address Offset:
Default Value:
Access:
4Fh
00h
Read/Write
The ACON Register enables and disables features related to PCI arbitration and PCI 2.1 compliance.
Bit
Description
7
Extended CPU-to-PIIX4 PHLDA# Signaling Enable (XPLDE).
When XPLDE=1,
the MTXC adds
the following additional signaling to signal PHLDA# (i.e., in addition to the normal CPU/PIIX4
PHOLD/PHLDA# protocol):
1. Whenever the North bridge begins a PCI read/write transaction, it will assert PHLDA# for
1 PCLK within the address phase of the transaction.
2. If the CPU is attempting a LOCKed cycle AND LOCK has been established (i.e. PLOCK# was
seen negated in address phase), the PHLDA# remains asserted for one additional clock following
the address phase.
This bit should be set to 1 anytime both Passive Release and Delayed Transaction are enabled in
the PIIX4. Passive release and delayed transaction are enabled via bits 1 and 0 in PIIX4 register 82h
(function 0). When bit 7 in this register is set to 1 (enabled), Bit 7 in PIIX4 Register, 6A (Function 0)
must also be set to 1. When enabling these two bits, enable Bit 7 in the PIIX4 first, followed by bit 7
in this register. When disabling these two bits, disable Bit 7 in this register first, followed by bit 7 in
the PIIX4.
6:0
Reserved.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 82443MX | PCIset |
| 82443ZX | Intel㈢ 440ZX AGPset: Host Bridge/Controller |
| 82451NX | Intel 450NX PCIset |
| 82452NX | Intel 450NX PCIset |
| 82453NX | Intel 450NX PCIset |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82439TXC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:INTEL 430HX PCISET 82439HX SYSTEM CONTROLLER (TXC) |
| 8243-A-0632-0 | 制造商:AMATOM ELECTRONIC HARDWARE 功能描述: |
| 8243-W | 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類別:靜電控制，ESD，無塵室產(chǎn)品 >> 處理劑，清潔劑，擦拭布 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 處理劑/清潔劑類型:清潔布 使用:電子設(shè)備 技術(shù)規(guī)格:無絨毛，微纖維 數(shù)量:100（12" L x 12" W） 包裝:袋 |
| 8243-W X(25) | 功能描述:化學(xué)物質(zhì) OPTICAL WIPE 25 PER BOX RoHS:否 制造商:3M Electronic Specialty 產(chǎn)品:Adhesives 類型:Epoxy Compound 大小:1.7 oz 外殼:Plastic Tube |
| 8243-WX25 | 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類別:靜電控制，ESD，無塵室產(chǎn)品 >> 處理劑，清潔劑，擦拭布 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 處理劑/清潔劑類型:清潔布 使用:電子設(shè)備 技術(shù)規(guī)格:無絨毛，微纖維 數(shù)量:100（12" L x 12" W） 包裝:袋 |
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