參數(shù)資料
型號(hào)： 82439TX
廠商： INTEL CORP
元件分類： 存儲(chǔ)控制器/管理單元
英文描述： System Controller(系統(tǒng)控制器)
中文描述： 256M X 8, DRAM CONTROLLER, PBGA324
封裝： BGA-324
文件頁(yè)數(shù)： 35/83頁(yè)
文件大?。?/td> 461K
代理商： 82439TX
E
82439TX (MTXC)
35
PRELIMINARY
Table 5. Attribute Definition
Read/Write
Attribute
Definition
Read Only
Read cycles: CPU cycles are serviced by the DRAM in a normal manner.
Write cycles: CPU initiated write cycles are ignored by the DRAM interface as well as the
cache. Instead, the cycles are passed to PCI for termination.
Areas marked as Read Only are L1 cacheable for Code accesses only. These regions are
not cached in the second level cache.
Write Only
Read cycles: All read cycles are ignored by the DRAM interface as well as the second
level cache. CPU-initiated read cycles are passed onto PCI for termination. The write only
state can be used while copying the contents of a ROM, accessible on PCI, to main
memory for shadowing, as in the case of BIOS shadowing.
Write cycles: CPU write cycles are serviced by the DRAM and L2 cache in a normal
manner.
Read/Write
This is the normal operating mode of main memory. Both read and write cycles from the
CPU and PCI are serviced by the DRAM and L2 cache interface.
Disabled
All read and write cycles to this area are ignored by the DRAM and cache interface. These
cycles are forwarded to PCI for termination.
Each PAM Register controls two regions, typically 16 Kbytes in size. Each of these regions has a 4-bit field. The
four bits that control each region have the same encoding and are defined in Table 6.
PCI master access to DRAM space is also controlled by the PAM Registers. If the PAM programming indicates
a region is writeable, then PCI master writes will be accepted (DEVSEL# generated). If the PAM programming
indicates a region is readable, PCI master reads will be accepted. If a PCI write to a non-writeable DRAM region,
or a PCI read to a non-readable DRAM region is seen, the MTXC will not accept the cycle (DEVSEL# will not be
asserted). PCI master accesses to enable memory hole regions will not be accepted.
Table 6. Attribute Bit Assignment
Bits [7, 3]
Reserved
Bits [6, 2]
Cache Enable
Bits [5, 1]
Write Enable
Bits [4, 0]
Read Enable
Description
x
x
0
0
DRAM disabled, accesses directed
to PCI
x
0
0
1
read only, DRAM write protected,
non-cacheable
x
1
0
1
read only, DRAM write protected, L1
cacheable for code accesses only
x
0
1
0
write only
x
0
1
1
read/write, non-cacheable
x
1
1
1
read/write, cacheable
As an example, consider a BIOS that is implemented on the expansion bus. During the initialization process the
BIOS can be shadowed in main memory to increase the system performance. When a BIOS is shadowed in
main memory, it should be copied to the same address location. To shadow the BIOS, the attributes for that
address range should be set to write only. The BIOS is shadowed by first doing a read of that address. This read
is forwarded to the expansion bus. The CPU then does a write of the same address, which is directed to main
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