參數(shù)資料
型號: W83C554F
英文描述: W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述: W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(南橋)
文件頁數(shù): 97/159頁
文件大?。?/td> 3991K
代理商: W83C554F
W83C553F
4.2.2
Electrical Specifications
WINBOND SYSTEMS LABORATORY
94
Programmable Interrupt Controller (PIC) Registers
Initialization Command Word 1 Register (default = 19h)
Function
:
A write to the Initialization Command Word 1 (ICW1) Register starts the interrupt controller
initialization sequence. Addresses 20h and A0h are referred to as the base address of Interrupt
Controllers #1 and #2 respectively. An I/O write to the Interrupt Controller #1 or #2 base address, with
bit 4 equal to "1," is interpreted as ICW1. For W83C553F based ISA systems, three I/O writes to "base
address +1" must follow the ICW1 to perform writes to ICW2, ICW3 and ICW4.
Type
:
Write Only
Bit Description
:
Bits [7:5]:
Reserved. These bits are not needed by the W83C553F and should be "000" while
programming.
Bit 4:
ICW1SEL. This bit must be a "1" to select ICW1. After the fixed initialization sequence to
ICW1, ICW2, ICW3 and ICW4, the controller base address is used to write to OCW2 and
OCW3. Bit 4 is "0" on writes to these registers.
Bit 3:
LTIM. This bit is always ignored and read as a "1."
Bit 2:
Reserved (ADI). This bit is ignored by the W83C553F.
Bit 1:
SNGL. This bit must be programmed to a "0," indicating the two interrupt controllers are
operating in cascade mode.
Bit 0:
IC4. ICSW4 Write Required. This bit must be set to a "1," indicating the ICW4 needs to be
programmed (that is, the controllers are operating in an x86 type system).
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