參數(shù)資料
型號: W83C554F
英文描述: W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述: W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(biāo)(南橋)
文件頁數(shù): 28/159頁
文件大?。?/td> 3991K
代理商: W83C554F
W83C553F
Pin Descriptions
WINBOND SYSTEMS LABORATORY
25
Table 2-6. X Bus Signals
Pin Name
SECURITY /
XRD#
Pin #
Input/
Output
Description
X Bus Read. When active "0", data flows from XD to SD. When
the W83C553F is in PowerPC mode, this pin is sampled after reset
and its value is reflected in bit 2 of the Port 92 register (see page
107).
Keyboard Controller Interrupt.
Real Time Clock Interrupt.
X Bus Buffer Enable. This signal enables an external X-bus buffer
whenever an X-bus device is decoded. This pin is a strap pin, needs
a 2.2k Ohm resistor pull up, otherwise will be in test mode.
This is a multi-function pin. When the W83C553F is in PowerPC
mode, this pin functions as the chip select for an external ROM,
using default ISA memory cycle timing. When the W83C553F is in
x86 mode, this pin functions as the lower bit of the X-bus Address.
This is a multi-function pin. When the W83C553F is in PowerPC
mode, this pin functions as the chip select for ports in the 800h-
8FFh I/O address range. When the W83C553F is in x86 mode, this
pin functions as the upper bit of the X-bus Address. In x86 mode,
an external decoder is required to decode the chip selects for X-bus
devices:
XCS[1:0]
Device
00
Idle
01
RTC Address Latch
10
RTC Data Port
11
ROM/BIOS or Keyboard Controller
116
Output/
Input
IRQ1
121
Input
IRQ8#
120
Input
XOE#
117
Output/
Input
XCS0/
ROMCS
119
Output
XCS1/X8XCS
118
Output
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