參數(shù)資料
型號: W83C554F
英文描述: W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述: W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(biāo)(南橋)
文件頁數(shù): 29/159頁
文件大?。?/td> 3991K
代理商: W83C554F
W83C553F
Pin Descriptions
WINBOND SYSTEMS LABORATORY
26
Table 2-7. CPU Interface and Miscellaneous Signals
Pin Name
Pin #
Input/
Output
Output
Description
Interrupt. Interrupt signal from the W83C553F interrupt controller to the
CPU.
Non-Maskable Interrupt.
It functions as Initialize CPU/Software Reset (INIT) when the W83C553F
is in x86 mode, as determined by pin 8 strapping after reset. INIT is
asserted for four PCI clocks following one of these events:
- Hot Reset bit set (port 92, bit 0)
- CPU Shutdown Cycle
- keyboard Reset Emulation bit is set (bit 1, Index 4E)
Speaker Data. This output drives an externally buffered speaker.
Power good signal from the power supply. This signal is used to generate
other reset signals to reset the system.
This multi-function pin's default function is Interrupt Request 13 (IRQ13).
The Numerical Co-processor Error (FERR#) function may be enabled by a
bit in the Function 0 PCI Configuration Space AT System Control Register
(Index 4Eh, bit 4).
This multi-function pin functions as Ignore Numeric Error (IGNNE#)
when the W83C553F is in x86 mode as determined by pin 8 strapping after
reset. It functions as HRESET# when the W83C553F is in PowerPC
mode. For connection to the PowerPC, HRESET# is asserted for a
duration of one millisecond after one of the following events:
- PWRGD active edge
- Hot Reset bit set (port 92, bit 0)
- CPU Shutdown Cycle
- Keyboard Reset Emulation bit is set (bit 1, Index 4E)
INT
10
NMI
11
Output
INIT
3
Output
SPKR
134
Output
PWRGD
2
Input
FERR#/IRQ13
12
Input
IGNNE# /
HRESET#
4
Output
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