參數(shù)資料
型號(hào): W83C554F
英文描述: W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述: W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(biāo)(南橋)
文件頁數(shù): 26/159頁
文件大?。?/td> 3991K
代理商: W83C554F
W83C553F
Pin Descriptions
WINBOND SYSTEMS LABORATORY
23
Table 2-5 (Continued). ISA Bus Signals
Input/
Output
Description
Input/
Output
transfer cycle beyond the default ready timer expiration.
Output
Bus Address Latch Enable. This signal indicates that a valid
address is on the bus.
Output
Address Enable. AEN is asserted during DMA cycles to prevent
I/O devices from misinterpreting the cycle as a valid I/O cycle.
Output
Termination Count. This signal is asserted to indicate that a DMA
channel's word count has reached terminal count.
Input
DMA Request. DMA service request from the DMA controllers.
Pin Name
IOCHRDY
Pin #
135
I/O Channel Ready. This signal is used by ISA slaves to extend the
BALE
168
AEN
136
TC
166
DRQ[7:5, 3:0]
1,203,198,
191,190,
193,196
194,192,
195
DAK[2:0]
Output
Encoded DMA Acknowledge. The channel number of the
arbitration winner is encoded in binary. An external decoder is
required to generate DACK[7:5, 3:0]#. The inactive value is 100b.
Interrupt Request.
IRQ[15, 14, 12:9,
7:3]
186,188,
183,181,
179,127,
154,157,
159,161,
163
Input
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