參數(shù)資料
型號: W83C554F
英文描述: W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述: W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(南橋)
文件頁數(shù): 103/159頁
文件大小: 3991K
代理商: W83C554F
W83C553F
Electrical Specifications
WINBOND SYSTEMS LABORATORY
100
Operational Control Word 1 Register
Function
:
The Operational Control Word 1 (OCW1) Register sets and clears the mask bits in the Interrupt Mask
(IMR) Register. Each interrupt request line may be selectively masked or unmasked any time after
initialization.
Type
:
Read/Write
Bit Description
:
Bits [7:0]:
IMR[7:0]. When a "1" is written to any bit in this register, the corresponding IRQx line is
masked. When a "0" is written to any bit in this register, the corresponding IRQx mask bit is
cleared and interrupt requests will again be accepted by the controller.
Note: Masking IRQ2 on 21h will also mask interrupt requests from A1h, which is physically
cascaded to IRQ2.
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