參數(shù)資料
型號: W83C554F
英文描述: W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述: W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(biāo)(南橋)
文件頁數(shù): 153/159頁
文件大?。?/td> 3991K
代理商: W83C554F
W83C553F
Timing Diagrams
WINBOND SYSTEMS LABORATORY
150
Table 6-8 (continued). Multiword DMA ATA Data Transfer Timing
Parameter
Values
Min
0ns
0ns
0ns
Max
Notes
tI
tJ
tKr IDEIOR[A:B]# negated
pulse width
IDEDAK[A:B]# to
IDEIOR[A:B]# /
IDEIOW[A:B]#
setup
Mode 0
Mode 1
Mode 2
Mode 3
IDEIOR[A:B]# /
IDEIOW[A:B]# to
IDEDAK[A:B]#
hold
Mode 0
Mode 1
Mode 2
Mode 3
20ns
5ns
5ns
Mode 0
Mode 1
Mode 2
Mode 3
50ns
50ns
25ns
The delay from DIOR# or DIOW# until the
state of IORDY is first sampled. If IORDY
is inactive, then the host shall wait until
IORDY is active before the PIO cycle can be
completed. If the device is not driving
IORDY negated at the time tA after the
activation of DIOR# or DIOW#, then t5
shall be met and tRD is not applicable. If
the device is driving IORDY negated at the
time tA after the activation of DIOR# or
DIOW#, then tRD shall be met and t5 is not
applicable.
tKw IDEIOW[A:B]# negated
pulse width
tLr IDEIOR[A:B]# to
IDEDRQ[A:B] delay
tLw IDEIOW[A:B]# to
IDEDRQ[A:B] delay
Mode 0
Mode 1
Mode 2
Mode 3
215ns
50ns
25ns
Mode 0
Mode 1
Mode 2
Mode 3
120ns
40ns
35ns
Mode 0
Mode 1
Mode 2
Mode 3
40ns
40ns
35ns
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