參數(shù)資料
型號: W83C554F
英文描述: W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述: W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(biāo)(南橋)
文件頁數(shù): 77/159頁
文件大小: 3991K
代理商: W83C554F
W83C553F
Electrical Specifications
WINBOND SYSTEMS LABORATORY
74
Level 1 Arbiter
There are two control bits for bank 1,2,3 modules. The "pfix" bit determines the fixed priority of the bank. The "protat" bit
determines whether to rotate the priority scheme of the bank after a grant is given. If the "protat" bit is not set, the arbiter will
give one request line higher priority ALL THE TIME. If the "protat" bit is set, the priority of the request lines are rotated
after each grant to the higher priority line. For bank 0, the "pfix" value is fixed to 0 and the "protat" value is fixed to 0 also.
pfix = 0
Bank 1
SIOREQ# > REQ0#
REQ0# > SIOREQ#
Bank 2
REQ1# > REQ2#
REQ2# > REQ1#
Bank 3
CPUREQ# > REQ3#
Level 2 Arbiter
For bank 4, there are 2 bits, "fpmod[1:0]", indicating the fixed priority of the bank. There is one bit, "bk4rc", controlling the
rotation of priority schemes. There are a total of 4 priority schemes each. A total of 8 slots are available on the round-robin
rotation. 4 slots are assigned with a priority scheme each. 4 other slots are programmable with selected priority schemes.
fpmod[1:0]
Priority Schemes
00
IDEREQ# > bk1win > bk3win
pfix = 1
REQ3# > CPUREQ#
Slots
Bank 0
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