參數(shù)資料
型號: W83C554F
英文描述: W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述: W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(南橋)
文件頁數(shù): 27/159頁
文件大?。?/td> 3991K
代理商: W83C554F
W83C553F
Pin Descriptions
WINBOND SYSTEMS LABORATORY
24
Table 2-5 (Continued). ISA Bus Signals
Input/
Output
Description
Output
This multi-function pin functions as ISA Reset when the
W83C553F is in PowerPC mode, as determined by pin 8 strapping
after power-up. It is driven for one millisecond duration after one of
the following conditions:
- PWRGD active edge
- Hot Reset bit set (port 92, bit 0)
- Reset Drive bit set (Clock Divisor Register bit 3)
ISA Reset is the inverted logical equivalent of PCI Reset.
When the W83C553F is in x86 mode, this pin functions as Power
Management Active. It is the output signal to the CPU bridge
which indicates the system activity status by becoming active when
a break event has occurred. Break events are programmed into PCI
Configuration Registers index 60h - 63h.
Input /
Output
Pin Name
PMACT# /
ISARST
Pin #
5
SD[15:0]
208-204,
202,199,
197,123,
125,126,
128-131,
133
Bidirectional Data Bus.
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