參數(shù)資料
型號: W83C554F
英文描述: W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述: W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(南橋)
文件頁數(shù): 47/159頁
文件大?。?/td> 3991K
代理商: W83C554F
W83C553F
3.14.4
The main arbiter can void the PCI GNT# signal sent to the W83C553F, if the current bus cycle takes too long, as in the case
of DMA bursts. When PCI GNT# is removed, and the value in the Latency Timer Register has reached zero, the W83C553F
will finish the current transfer, and immediately release the bus. The timer in the W83C553F PCI configuration space is
programmable. The W83C553F will keep PCI REQ# asserted to regain bus ownership.
Electrical Specifications
WINBOND SYSTEMS LABORATORY
44
PCI Preemption Timing
Figure 3-12. Preemption Timing
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