參數(shù)資料
型號： W83C554F
英文描述： W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述： W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(biāo)（南橋）
文件頁數(shù)： 49/159頁
文件大小： 3991K
代理商： W83C554F
W83C553F
3.15 IDE Interface Operation
Operation of the IDE interface is controlled by the configuration registers. Port 0 (Primary Port) and Port 1 (Secondary Port)
have the same features, capabilities and configuration options. All 8-bit timing is fixed. The following table shows the 8-bit
fixed timing.
Although the 16-bit timing (host cycle 16/32-bit) is programmable on a cycle basis (on/off time), most of the 16-bit cycle
timing is also fixed. Address setup, address hold, and data hold (write) times will be the same as for the 8-bit cycles. Data
setup time will be equal to the write command on time. This allows the user to only program the command on/off times to
select PIO Mode 0, 1, 2, 3, 4 or 5 (proposed), and DMA Single and Multiword 0, 1 or 2 timing.
Much of the DMA mode timing is also fixed. When DMA transfers are executed on the IDE interface, the selected ports'
chip selects (IDECS0# and IDECS1# for primary and secondary) will be de-asserted (high) when the BMEN bit in the
associated Bus Master Control Register is set to "1." When the IDE device asserts IDEDRQ[A:B], the W83C553F will
immediately assert IDEDAK[A:B]# if BMEN is set. One clock later the IDEIOW[A:B]# or IDEIOR[A:B]# output will be
asserted. For multiword DMA transfers, the IDEIOW[A:B]# or IDEIOR[A:B]# signal will free run at the programmed rate
as long as DRQ remains asserted and the W83C553F is prepared to complete a data transfer. If IDEDRQ[A:B] has not de-
asserted by the rising edge of the IDEIOW[A:B]# or IDEIOR[A:B]# signal multiword DMA is assumed and at least one
more cycle will be executed. If DRQ de-asserts at any time after IDEDAK[A:B]# is asserted but before IDEIOW[A:B]# or
IDEIOR[A:B]# is de-asserted, this will be the last cycle until DRQ re-asserts. In this case, IDEDAK[A:B]# will be de-
asserted one clock after the IDEIOW[A:B]# or IDEIOR[A:B]# signal de-asserts. This allows for the support of the single
and multiword DMA cycles automatically.
Table 3-3 Eight-bit Fixed Timing
Parameter
Electrical Specifications
WINBOND SYSTEMS LABORATORY
46
Time (CLKs)
SPD ="1"
10
10
3
1
3
1
20
Command on
Command off
Address setup
Address hold
Data setup (wr)
Data Hold (wr)
Cycle time
If CLK < 33 MHz, then the timing in Table 3-3 is ATA Mode 0 compatible.
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