參數(shù)資料
型號(hào)： W83C554F
英文描述： W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述： W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(biāo)（南橋）
文件頁(yè)數(shù)： 6/159頁(yè)
文件大小： 3991K
代理商： W83C554F
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W83C553F
TABLE OF CONTENTS
Preface
............................................................................................................................................... 1
1.0
General Information................................................................................................... 5
1.1
Features .................................................................................................................... 5
1.2
General Description................................................................................................... 7
1.3
Stylistic Conventions Used in this Manual.................................................................. 9
2.0
Pin Descriptions
................................................................................................................... 10
2.1
Pin Assignments........................................................................................................ 10
2.2
Pin Description........................................................................................................... 13
3.0
System Architecture
............................................................................................................. 28
3.1
Overview................................................................................................................... 28
3.2
Active State............................................................................................................... 29
3.3
Bus Structures ........................................................................................................... 30
3.4
PCI-to-ISA Bridge...................................................................................................... 31
3.5
PCI Bus Cycles.......................................................................................................... 31
3.6
PCI I/O Read Cycle ................................................................................................... 34
3.7
PCI I/O Write Cycle ................................................................................................... 35
3.8
PCI Configuration Read Cycle ................................................................................... 36
3.9
PCI Configuration Write Cycle................................................................................... 37
3.10
PCI Memory Read ..................................................................................................... 38
3.11
PCI Memory Write..................................................................................................... 39
3.12
PCI Memory Read Line.............................................................................................. 40
3.13
PCI Memory Write and Invalidate.............................................................................. 40
3.14
Transaction Termination ............................................................................................ 41
3.14.1
PCI Disconnect With Data Transfer Timing................................................ 41
3.14.2
PCI Disconnect Without Data Transfer Timing ........................................... 42
3.14.3
PCI Target Abort Timing ............................................................................ 43
3.14.4
PCI Preemption Timing.............................................................................. 44
3.14.5
PCI Master Abort Timing............................................................................ 45
3.15
IDE Interface Operation............................................................................................. 46
3.16
PIO Transfers ............................................................................................................ 47
3.17
32-Bit Data Transfers................................................................................................. 48
3.18
Bus Master Transfers................................................................................................. 49
3.19
82C59A Interrupt Controller ....................................................................................... 49
3.20
82C37A DMA Controller............................................................................................. 49
3.21
82C54 Counter/Timer ................................................................................................ 50
3.22
PCI Arbiter................................................................................................................. 50
3.23
Break Events............................................................................................................. 51
3.24
CPU Modes (X86 or PowerPC) .................................................................................. 51
4.0
Register Information
............................................................................................................ 52
4.1
PCI Configuration Space - ISA Bridge Registers (Function 0) .................................... 54
4.1.1
Function 0 Header Registers...................................................................... 54
4.1.2
Function 0 Control Registers...................................................................... 58
4.2
ISA Bridge (Function 0) I/O Registers ........................................................................ 78
4.2.1
DMA Controller I/O Registers..................................................................... 78
4.2.2
Programmable Interrupt Controller (PIC) Registers .................................... 93
4.2.3
Counter/Timer I/O Registers....................................................................... 101
4.2.4
Miscellaneous I/O Control Registers........................................................... 105
4.3
PCI Configuration Space - Bus Master IDE Registers (Function 1)............................ 109
4.3.1 Function 1 Header Registers............................................................................. 111
Table of Contents
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