參數(shù)資料
型號: W83C554F
英文描述: W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述: W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(biāo)(南橋)
文件頁數(shù): 102/159頁
文件大?。?/td> 3991K
代理商: W83C554F
W83C553F
Electrical Specifications
WINBOND SYSTEMS LABORATORY
99
Initialization Command Word 4 Register
Function
:
Both interrupt controllers must have the Initialization Command Word 4 (ICW4) Register programmed
as part of their initialization sequence. At a minimum, bit 0 must be set to "1" to indicate it is operating
in an x86-based system.
Type
:
Write Only
Bit Description
:
Bits [7:5]:
Reserved. These bits must be programmed to "000."
Bit 4:
SFNM. Special Fully Nested Mode. This mode should normally be disabled by writing "0" to
this bit.
Bit 3:
BUF. Buffered Mode. This bit must be programmed to "0" for the W83C553F.
Bit 2:
MNS. Master/Slave in Buffered Mode. This bit must be programmed to "0" for the W83C553F.
Bit 1:
AEOI. Automatic End of Interrupt. This bit should normally be programmed to "0." If
programmed to "1," Automatic End of Interrupt Mode is enabled.
Bit 0:
UPM. Microprocessor Mode. This bit must be set to "1" to indicate the interrupt controller is
operating in an x86-based system.
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