參數(shù)資料
型號: W83C554F
英文描述: W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述: W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(biāo)(南橋)
文件頁數(shù): 46/159頁
文件大?。?/td> 3991K
代理商: W83C554F
W83C553F
3.14.3
The Target Abort cycle of Figure 3-11 starts when the target asserts DEVSEL# for one clock, then de-asserts DEVSEL# and
asserts STOP#. A target can use this sequence to indicate it cannot service the data transfer, and does not want the
transaction retried. The W83C553F cannot assume any data transfers in the current transaction were successful. It
terminates the current transfer with the de-assertion of FRAME#, and IRDY#. Since data integrity is not guaranteed, the
W83C553F cannot recover from a target abort event. Any on-going IDE activity will be stopped immediately, and an
interrupt will be generated if enabled. Abort and Error bits in the DMA Status register will be set. The PCI Configuration
registers will not be cleared. The PCI Configuration Space Status Register's RTA bit will be set to indicate the W83C553F
has received a Target Abort.
Electrical Specifications
WINBOND SYSTEMS LABORATORY
43
PCI Target Abort Timing
Figure 3-11. Target Abort Timing
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