參數(shù)資料
型號: W83C554F
英文描述: W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述: W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(biāo)(南橋)
文件頁數(shù): 95/159頁
文件大?。?/td> 3991K
代理商: W83C554F
W83C553F
Electrical Specifications
WINBOND SYSTEMS LABORATORY
92
Scatter/Gather Status Registers
Type:
Bit Description:
Bit 7:
Bit 6:
Bit 5:
Read only
NEXT_LINK_NULL. Next Link Null Indicator.
Reserved.
ISSUE_IRQ13_EOP. Issue IRQ13 on last buffer. When bit 5 = 0, EOP is issued on last buffer;
when bit 5 = 1, IRQ13 is issued.
Reserved.
SG_BASE_REQ_FULL. Scatter/Gather Base Register Status. When bit 3 = 0, the base
register is empty; when bit 3 = 1, the base register has a buffer link loaded.
SG_CUR_REG_FULL. Scatter/Gather Current Register Status. When bit 2 = 0, the current
register is empty; when bit 2 = 1, the current register has a buffer link loaded.
Reserved.
SG_ACTIVE. Scatter/Gather Active. This bit indicates the current Scatter/Gather transfer
status. Bit 0 is set to 1 after a Scatter/Gather Start Command is issued. When bit 0 = 0, it
means there is no Scatter/Gather operation.
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
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