參數(shù)資料
型號: W83C554F
英文描述: W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述: W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(南橋)
文件頁數(shù): 59/159頁
文件大?。?/td> 3991K
代理商: W83C554F
W83C553F
Electrical Specifications
WINBOND SYSTEMS LABORATORY
56
Status Register (default = 0200h)
Type:
Bit Description
:
Bit 15:
Bit 14:
Bit 13:
Bit 12:
Bit 11:
Bits [10:9]:
Bit 8:
Bit 7:
Read/Write
Detected Parity Error (DPE). This bit is read/write.
Signaled System Error (SSE).
Received Master Abort (RMA). This bit is read/write.
Received Target Abort (RTA). This bit is read/write.
Signaled Target Abort (STA). This bit is read/write.
DEVSEL# Timing (DVSLT). Medium speed. These read only bits are both set to "01".
Master Data Parity Error Detected (MDPE). This bit is read/write.
Fast Back-to-Back Capable (FB2BC). W83C553F does not decode fast back-to-back cycles
across different targets. This read only bit is set to "0".
UDF Supported (UDFS). W83C553F does not support user definable features. This read only
bit is set to "0".
66 MHz Capable (PCI66C). W83C553F does not support 66 MHz bus speed. This read only
bit is set to "0".
Reserved. This read only bit is set to "0".
Bit 6:
Bit 5:
Bits [4:0]:
Signaled Target Abort
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