參數(shù)資料
型號: W83C554F
英文描述: W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述: W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(南橋)
文件頁數(shù): 71/159頁
文件大?。?/td> 3991K
代理商: W83C554F
W83C553F
Electrical Specifications
WINBOND SYSTEMS LABORATORY
68
AT System Control Register (default = 04h)
Type:
Read/Write
Bit Description
:
Bit 7:
Reserved.
Bit 6:
ISA Refresh Enable.
Bit 5:
Reserved, always 0.
Bit 4:
FERR# Enable. If this bit is set to "1," pin 12 will function as the Numeric Co-processor error
input.
Bit 3:
Reserved.
Bit 2:
P92E. Port 92 Enable. When enabled, access to Port 92 is enabled. When disabled, cycle will
be passed to the ISA bus.
Bit 1:
Keyboard RC Emulation Enable. In x86 mode, this bit decodes the keyboard reset command
and generates INIT for at more than 4 PCI clocks. In PowerPC mode, this bit decodes the
keyboard reset command and generates HRESET# for 1ms.
Bit 0:
Keyboard Gate A20 Emulation Enable. This bit toggles the Gate A20 output in x86 mode,
depending on the keyboard command.
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