參數(shù)資料
型號: W83C554F
英文描述: W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述: W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(biāo)(南橋)
文件頁數(shù): 101/159頁
文件大?。?/td> 3991K
代理商: W83C554F
W83C553F
Electrical Specifications
WINBOND SYSTEMS LABORATORY
98
Initialization Command Word 3 Register - PIC 1 (Master, default = 04h)
Function
:
On the Interrupt Controller #1 (the master controller), this register indicates which IRQ line physically
connects the INT output of Interrupt Controller #2 (PIC 2) to Interrupt Controller #1 (PIC 1).
Type
:
Write Only
Bit Description
:
Bits [7:3]:
SLAVE[7:3]. These bits must be programmed to "00000."
Bit 2:
SLAVE2. Cascaded Interrupt Controller IRQ Connection. This bit must always be programmed
to "1." It indicates the slave controller (#2) is cascaded on IRQ2.
Bits [1:0]:
SLAVE[1:0]. These bits must be programmed to "00."
Initialization Command Word 3 Register - PIC 2 (Slave)
Function
:
On the Interrupt Controller #2 (the slave controller), this register contains the slave identification code
broadcast by Interrupt Controller #1 from the trailing edge of the first INTA# pulse to the trailing edge of
the second INTA# pulse. It must be programmed to 02h for Interrupt Controller #2.
Type
:
Write Only
Bit Description
:
Bits [7:3]:
Reserved. These bits must be programmed to "00000."
Bits [2:0]:
SLVID[2:0]. Slave Identification Code. During the initialization sequence, bits 2 and 0 must be
programmed to "0" and bit 1 programmed to a "1."
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