參數(shù)資料
型號(hào): W83C554F
英文描述: W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述: W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(biāo)(南橋)
文件頁數(shù): 23/159頁
文件大小: 3991K
代理商: W83C554F
W83C553F
Pin Descriptions
WINBOND SYSTEMS LABORATORY
20
Table 2-4 (continued). IDE Interface Bus Signals
Pin Name
IDEDRQA
Pin #
Input/
Output
Description
DMA Request A. This signal is the primary port DMA handshake
from the IDE device. When asserted, it indicates a data transfer is
requested.
DMA Acknowledge A. This is the primary port DMA handshake to
the IDE device. When asserted, it indicates a data transfer can be
executed.
DMA Request B. This is the secondary port DMA handshake from
the IDE device. When asserted, it indicates a data transfer is
requested.
DMA Acknowledge B. This is the secondary port DMA handshake
to the IDE device. When asserted, it indicates a data transfer can be
executed.
IDE Drive Address.
IDE Drive Data. 16-bit bi-directional bus.
97
Input
IDEDAKA#
94
Output
IDEDRQB
96
Input
IDEDAKB#
93
Output
DA[2:0]
88,90,89
98,101,103,
105,108,
110,112,
114,115,
113,111,
109,106,
104,102,
100
95
Output
DD[15:0]
Input/
Output
IDECHRDY
Input
IDE I/O Channel Ready. When IDECHRDY is negated, the current
cycle will be extended. This input is connected to the primary port,
and can also be connected to the secondary port.
IDE IRQ B. Secondary port interrupt request.
IDE IRQ A. Primary port interrupt request.
IDEIRQB
91
Input
IDEIRQA
92
Input
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