參數(shù)資料
型號: W83C554F
英文描述: W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述: W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(biāo)(南橋)
文件頁數(shù): 75/159頁
文件大小: 3991K
代理商: W83C554F
W83C553F
Electrical Specifications
WINBOND SYSTEMS LABORATORY
72
Additional Break Event Enable Register (default = 00h)
Function:
This power management register may only be used while the W83C553F is in x86 mode.
Type
:
Read/Write
Bit Description
:
Bit 7:
Reserved.
Bit 6:
PCI SERR#. SERR Detection Enable. When this bit is "1," SERR detection is enabled. Upon
detection, the PMU will de-assert PMACT#.
Bit 5:
IRQ0CLR. IRQ0 Clear. To clear IRQ0, write a "1", followed by a "0", to this bit.
Bit 4:
ISA IOCHK#. IOCHK Detection Enable. When this bit is "1," IOCHK detection is enabled.
Upon detection, the PMU will de-assert PMACT#.
Bit 3:
PCI PERR#. PERR Detection Enable. When this bit is "1," PERR detection is enabled. Upon
detection, the PMU will de-assert PMACT#.
Bit 2:
NMI. NMI Detection Enable. When this bit is "1," NMI detection is enabled. Upon detection,
the PMU will de-assert PMACT#.
Bit 1:
Interrupt. INTR Detection Enable. When this bit is "1," INTR detection is enabled. Upon
detection, the PMU will de-assert PMACT#.
Bit 0:
PMUMGEN. GLOBAL Enable of Break Events. When this bit is "1," GLOBAL break event
detection is enabled. Upon detection, the PMU will de-assert PMACT#.
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