- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄361795 > W83C554F W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208 PDF資料下載
參數(shù)資料
| 型號(hào)： | W83C554F |
| 英文描述： | W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208 |
| 中文描述： | W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(biāo)（南橋） |
| 文件頁數(shù)： | 53/159頁 |
| 文件大?。?/td> | 3991K |
| 代理商： | W83C554F |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁當(dāng)前第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁
W83C553F
3.21 82C54 Counter/Timer
One 82C54 counter/timer, with three channels, is included in the W83C553F. The clocks for the three channels are
connected to the 14.31818 MHz clock through a divide-by-twelve counter. The gate inputs of counters 0 and 1 are tied high
so that they are always enabled. The gate input of counter 2 is tied to bit 0 of Port B, inside the chip. The output of counter 0
is connected to the IRQ0 input of the interrupt controllers. The output of counter 1 goes to the arbitration logic for a refresh
request. Finally, the output of counter 2 goes to an AND gate, which drives the SPKR output pin. The other input to this
AND gate comes from bit 1 of Port B.
3.22 PCI Arbiter
The W83C553F contains a programmable, eight master PCI arbiter which can be tailored to meet system-specific arbitration
requirements. Pin 16 is available to strap the arbiter into its disabled state on power-up. A weak 2.2K ohm pull-down
resistor is recommended for this in systems using an external arbiter. When disabled, the "Function 0" ISA bridge uses the
REQ#/GNT# pair on pins 25 and 26, and the "Function 1" IDE uses the REQ#/GNT# pair on pins 27 and 28. If no pull-
down resistor is used on pin 16, the on-chip arbiter will "come up" enabled after power up.
When in the active state, the eight masters supported by the W83C553F are its two internal masters (ISA bridge and IDE),
the system CPU, and REQ#/GNT#[4:0] which are available to the system designer. The PCI5TH# function of pin 13 can be
used to change the fifth REQ#/GNT# pair (on pins 6 and 7) to FLSHREQ#/FLSHACK# if desired (in either CPU mode).
This PCI5TH# function is automatically overidden by the ARBDIS# pin when enabled.
FLSHREQ#/FLSHACK# are only used in Guaranteed Access Timing (GAT) mode. In GAT mode, before Function 0 makes
a request for the PCI bus, it asserts FLSHREQ# to the system and waits for FLSHACK# to be asserted. The system can use
this signal to flush all PCI buffers so that the W83C553F can be granted unimpeded access to main memory. When Function
0 (PCI-to-ISA bridge) is not in GAT mode, it behaves as any other PCI master device.
Upon power-up, the arbiter defaults to a "round-robin" rotation scheme allowing all PCI masters equal access to the local bus.
If desired, the relative priority of each REQ/GNT pair can be custom tailored to a specific system design via the PCI Priority
Control Register 1 at Index 80h in the Function 0 PCI Configuration Space. Note that all masters are assured of access to the
PCI bus at least once during each rotation regardless of the programming options chosen. (This is required for PCI
compliance, so no functions are "locked out" for an extended period).
Electrical Specifications
WINBOND SYSTEMS LABORATORY
50
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W83L519D | Peripheral Miscellaneous |
| W86C451 | UART |
| W86C452 | UART |
| W86F3448D | LC86F3548A |
| W86F3448M | LC86F3548A |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W83C554FY | 制造商:Nuvoton Technology Corp 功能描述:I/O Controller Phase Controller 制造商:Nuvoton Technology 功能描述:I/O Controller Phase Controller |
| W83E14 | 制造商:OMRON INDUSTRIAL AUTOMATION 功能描述:SYSMAC-C20 MANUAL DX CODE ZA |
| W83L177R | 制造商:WINBOND 制造商全稱:Winbond 功能描述:100MHZ 2-DIMM SDRAM BUFFER FOR NOTEBOOK |
| W83L197R-16 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:2-CHIP 100MHZ CLOCK FOR BX NOTEBOOK |
| W83L351 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ExpressCard⑩ Power Interface Switch |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。