參數(shù)資料
型號: W83C554F
英文描述: W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述: W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(biāo)(南橋)
文件頁數(shù): 143/159頁
文件大?。?/td> 3991K
代理商: W83C554F
W83C553F
Timing Diagrams
WINBOND SYSTEMS LABORATORY
140
Table 6-3. IDE Interface Timing
Parameter
Values
Max
Min
3 x
t1
ns -
30ns
0
.5 x
t1
ns
10ns
0ns
t19ns
30ns
300ns
r2 x t1ns
Notes
t11 Address Setup to command low
t12 Address hold from command high
t13 IDE_IOCHRDY high setup to command high
t14 Read data setup to IDE_IOR# high
t15 Read data hold from IDE_IOR# high
t16 Write data setup to IDE_IOW# high
t17 Write data hold from IDE_IOW# high
t18 Command recovery time 8-bit cycle
t18 Command recovery time 16-bit cycle
r2 is the 16-bit command
recovery count in PCI
clocks
(page 126)
t19 Command active time 8-bit cycle
t19 Command active time 16-bit cycle
300ns
a2 x t1ns
a2 is the 16-bit command
active count in PCI clocks
(page 126)
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