參數(shù)資料
型號: W83C554F
英文描述: W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述: W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(biāo)(南橋)
文件頁數(shù): 134/159頁
文件大?。?/td> 3991K
代理商: W83C554F
W83C553F
4.4.1
Electrical Specifications
WINBOND SYSTEMS LABORATORY
131
Primary/Secondary Command Registers
Primary/Secondary Command #1 Registers
Function
:
These registers are used to control DMA data transfers to/from the two IDE ports when multi-word DMA
disk drives are used.
Type
: Read/Write
Bit Description
:
Bits [7:4]:
These bits are hardwired to 0b.
Bit 3:
W/R#. This bit controls the bus master transfer direction. Low is PCI memory to IDE device and
high is IDE device to PCI memory. This bit must not be changed while the bus master function
is active as defined by bit 0.
Bits [2:1]:
These bits are hardwired to 0b.
Bit 0:
BMEN. Bus Master operation is active when this bit is set. The bus master operation can be
terminated by writing a 0b to this bit but is considered as an abort and can not be resumed.
Writing a 1b to this bit will also set the BMEN bit in the Device Control Register.
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