參數(shù)資料
型號: W83C554F
英文描述: W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述: W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(南橋)
文件頁數(shù): 51/159頁
文件大?。?/td> 3991K
代理商: W83C554F
W83C553F
3.17 32-Bit Data Transfers
32-bit data transfers are used to reduce system overhead and improve performance. The standard PIO protocol requires the
system CPU to execute an I/O cycle and a memory cycle to move two bytes of data between the IDE device and memory. To
transfer 4 bytes of data would require two I/O cycles and two memory cycles. This can be accomplished with one 32-bit I/O
and one 32-bit memory cycle. This cuts the CPU cycles in half. By enabling read ahead, the IDE read cycles will be
buffered from the PCI bus and execute in parallel with the system memory reads cutting overhead more. Enabling posted
writes will similarly improve write performance.
PCI Bus 32-Bit PIO Write Cycle
Electrical Specifications
WINBOND SYSTEMS LABORATORY
48
IDE Write Cycle with Posted Writes
PCI Bus 32-Bit PIO Read Cycle
IDE Read Cycle with Read Ahead
The two drawings shown above show the relationship
between the PCI bus and the IDE interface.
相關(guān)PDF資料
PDF描述
W83L519D Peripheral Miscellaneous
W86C451 UART
W86C452 UART
W86F3448D LC86F3548A
W86F3448M LC86F3548A
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