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參數(shù)資料
| 型號(hào)： | W83C554F |
| 英文描述： | W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208 |
| 中文描述： | W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(biāo)（南橋） |
| 文件頁(yè)數(shù)： | 129/159頁(yè) |
| 文件大?。?/td> | 3991K |
| 代理商： | W83C554F |
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W83C553F
Bit Description
:
Bit 31:
Bit 30:
Electrical Specifications
WINBOND SYSTEMS LABORATORY
126
Reserved. This bit is hardwired to 0b.
IDE_IRQB. This is the IDE_IRQB input signal. It reflects the unbuffered state of the IDE_IRQB
input.
Reserved. This bit is hardwired to 0b.
IDE_IRQA. This is the IDE_IRQA input signal. It reflects the unbuffered state of the IDE_IRQA
input.
Reserved. This bit is hardwired to 0b.
RA[10:0]. These bits control the read-ahead duration for the IDE interface. Read-ahead
duration is defined as the number of 16-bit IDE data reads that will be prefetched independent
of any PCI bus cycles. The actual read ahead count will equal the programmed value plus one
cycle. The default value is 0FFh (255 decimal + 1) for 256 16-bit IDE cycles (512 bytes).
Reserved. These bits are hardwired to 0000b.
LEGIRQ. This bit and bit 2 of the Programming Interface Register control the interrupt
destination for both the IDE ports, in association with function 0 IDE_Interrupt_Routing_Control
_Register (43H) . The default value of function 0, IDE Interrupt Routing Control Register is EFh,
indicating primary port interrupt goes to IRQ 14, and secondary interrupt goes to IRQ15. When
LEGIRQ=1, for using legacy interrupts, the function 0 IDE_Interrupt_Routing Control Register
should be programmed to value 0, indicating legacy interrupt internal routing to INTC# and/or
INTD# are desired, as shown below. The default state is 0b.
LEGIRQ
P1N/L#
IDEIRQA
0
x
IRQ14
1
0
INTC#
1
1
INTC#
Reserved. These bits are hardwired to 0b.
Reserved.
Reserved. This bit is hardwired to 0b.
P1F16. Port 1 Fast 16 controls the operation of Port 1 (secondary port) when executing 16 bit
PIO cycles on the PCI bus. When reset (0b), all 16 bit cycles to Port 1 will operate using the
default 8-bit timing (Mode 0 compatible). Also, posted writes, read ahead and IDE_IOCHRDY
will be disabled for 16-bit cycles. When set to 1b, 16-bit cycles will operate using the
programmed speed setting, while posted writes, read ahead, and IDE_IOCHRDY will be
supported as programmed in the applicable Port x Drive x Control Register. Bit 5 is cleared to
a 0b after reset or if the secondary port receives a soft reset, defined as any time the secondary
port device control register (default address 376h) is written with bit 2 a 1b.
P1EN. This is the secondary port enable bit. When set and IOEN is set in the Control Register,
I/O cycles to the secondary port will be claimed and executed. When 0b or IOEN is 0b, all
secondary port cycles will be ignored. The default value of this bit is "1."
Reserved. These bits are hardwired to 0b.
P0F16. Port 0 Fast 16 functions the same as bit 5, but for Port 0 (Primary Port). Similarly, this
bit is cleared any time the primary port device control register (default address 3F6h) is written
with bit 2 a 1b.
P0EN. This is the primary port enable bit. When set and IOEN in the Control Register is
enabled, I/O cycles to the primary port will be claimed and executed. When 0b or IOEN is 0b,
all primary port cycles will be ignored. The default value of this bit is 1b.
Bit 29:
Bit 28:
Bit 27:
Bits [26:16]:
Bits [15:12]:
Bit 11:
IDEIRQB
IRQ15
INTD#
INTC#
Bit [10:8]:
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit [3:2]:
Bit 1:
Bit 0:
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