參數(shù)資料
型號: W83C554F
英文描述: W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述: W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(biāo)(南橋)
文件頁數(shù): 122/159頁
文件大小: 3991K
代理商: W83C554F
W83C553F
Electrical Specifications
WINBOND SYSTEMS LABORATORY
119
PCI Base and Sub Class Register (default = 0101h)
Type:
Read only
Bit Description
:
Bits [15:8]:
Sub Class. Permanently defaults to 01h - “IDE Controller.”
Bits [7:0]:
Base Class. Permanently defaults to 01h - “Mass Storage Controller.”
Cache Line Size Register (default = 08h)
Function
:
This 8-bit register is programmed by the host to the cache line size being used by the system processor. It is
programmed in units of 32-bit double words. The programmed value effects the memory read and write
commands executed when the W83C553F is operating as a bus master. The default value is 08h. This
register can only be programmed to 04h (16 bytes), 08h (32 bytes), or 00h (4 bytes); all other values will be
ignored.
Type
: Read/Write
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